Pillar Transistor Layout for Reduced Chip Area and Diffusion Resistance
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Solution Overview
Problem
Semiconductor devices with pillar transistors face challenges in increasing integration density while minimizing area and reducing resistance, as the layout of pillar transistors can lead to increased area and resistance due to the arrangement of silicon pillars and diffusion layers.
Innovation Solution
The semiconductor device optimizes pillar transistor layout by arranging pillar rows such that the distance between silicon pillars is equal to or smaller than twice the thickness of the gate insulator film, and using a symmetric arrangement to reduce the area and complexity of gate lead wires, thereby reducing the area and resistance of the lower diffusion layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pillar transistors are arranged with larger spacing between silicon pillars, then manufacturing precision is improved, but area increases and integration density decreases
Solution Approach 1:
The patent applies parameter changes by precisely controlling the distance between adjacent silicon pillars to be equal to or smaller than twice the thickness of the gate insulator film. This optimization of the spacing parameter enables the gate electrode to properly cover the silicon pillar surfaces while minimizing the area occupied by each transistor, thereby resolving the contradiction between manufacturing precision and chip area.
2Area of stationary object
If pillar transistors are arranged with smaller spacing between silicon pillars, then area is reduced and integration density increases, but manufacturing precision and resistance control deteriorate
Solution Approach 1:
The patent establishes an optimal parameter range for the distance between silicon pillars (equal to or smaller than twice the gate insulator film thickness) that simultaneously achieves area reduction and maintains manufacturing precision. This precise parameter control ensures proper gate electrode coverage while minimizing transistor area, resolving the contradiction between area reduction and manufacturing precision.
3Adaptability or versatility
If asymmetric arrangement of pillar rows is used, then layout flexibility is improved, but device complexity and gate lead wire complexity increase
Solution Approach 1:
The patent employs asymmetric arrangement of pillar rows where the first and second pillar rows are positioned at different distances from the third pillar row. This asymmetric configuration provides layout flexibility for circuit design while the systematic ordering of rows maintains manageable complexity for gate lead wire routing, resolving the contradiction between adaptability and device complexity.
4Reliability
If larger area is allocated to lower diffusion layer, then resistance is reduced, but chip area increases
Solution Approach 1:
The patent merges the lower diffusion layers of multiple pillar transistors into a shared common lower diffusion layer. This consolidation reduces the total area required for lower diffusion layers while maintaining low resistance through the shared conductive path, effectively resolving the contradiction between resistance reduction and area minimization.
Data Source
AI summary
A first pillar transistor and a second pillar transistor are arranged with no other pillar transistor therebetween, a distance between a first silicon pillar in the first pillar transistor and a second silicon pillar in the second pillar transistor is smaller than a distance between a third silicon pillar in a third pillar transistor and the first silicon pillar.