Pillar-Type Storage Node Electrodes for High-Density Capacitors
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Solution Overview
Problem
As semiconductor memory devices increase in capacity and integration density, the area occupied by cell capacitors decreases, leading to challenges in maximizing capacitance with limited space, particularly due to increasing aspect ratios in three-dimensional structures.
Innovation Solution
A method is developed to form a high-capacitance capacitor by creating pillar-type storage node electrodes using support structures and mask patterns, which reduces the aspect ratio and facilitates easier filling with conductive material, while maintaining electrical connectivity to source and drain regions of a transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional cylindrical structure is adopted to increase electrode area, then capacitance is maximized in limited space, but the aspect ratio of the capacitor increases
Solution Approach 1:
The capacitor structure is segmented into multiple horizontal layers (first capacitor layer, second capacitor layer, third capacitor layer) stacked vertically. Each layer contains separate electrode structures (first electrode, second electrode, third electrode, fourth electrode) that can be independently formed and controlled. This segmentation allows the total capacitance to be distributed across multiple smaller capacitive elements rather than relying on a single high-aspect-ratio cylindrical structure.
Solution Approach 2:
The invention transitions from a vertical cylindrical geometry to a layered horizontal geometry. The electrode structures are formed as horizontal plates separated by dielectric layers, creating capacitors that extend in the lateral dimensions rather than relying on vertical height. This dimensional change reduces the aspect ratio while maintaining or increasing total capacitance through stacking multiple layers.
2Ease of manufacture
If the aspect ratio of the capacitor is reduced, then filling with conductive material becomes easier, but the electrode area may decrease
Solution Approach 1:
The total electrode area is segmented into multiple smaller electrode structures distributed across different horizontal layers. Each electrode (first, second, third, fourth electrodes) can be formed with moderate dimensions suitable for conventional filling processes, avoiding the need to fill a single tall cylindrical structure. The cumulative area of all electrodes across layers provides sufficient total capacitance.
Solution Approach 2:
The electrode structures are arranged in horizontal planes separated by dielectric layers, creating a multi-layer plate capacitor configuration. This allows the electrode area to be expanded laterally across multiple layers rather than vertically, making each individual electrode structure easier to fill while the stacked arrangement maintains large total effective area.
3Quantity of substance
If separate storage node electrodes are formed in each cell, then total capacitance increases, but the footprint of capacitors increases
Solution Approach 1:
Multiple capacitor layers are stacked vertically within the same lateral footprint area. The first, second, and third capacitor layers are positioned at different vertical levels, allowing separate storage node electrodes to be formed in each cell without proportionally increasing the horizontal footprint. This vertical stacking multiplies the effective capacitance within a compact footprint.
Solution Approach 2:
Multiple capacitor structures are merged into a single integrated vertical stack within each memory cell. The electrode structures from different layers are combined to form a unified capacitor assembly that provides increased total capacitance while occupying a compact footprint area. The shared lateral footprint contains multiple vertically-stacked capacitive elements.
Data Source
AI summary
A method of forming a semiconductor memory device includes sequentially forming an etch stop layer and then a mold layer, forming a plurality of line-shaped support structures and a first sacrificial layer filling gaps between the support structures on the mold layer, sequentially forming a plurality of line-shaped first mask patterns, a second sacrificial layer, and then second mask patterns on the support structures and on the first sacrificial layer, removing the second sacrificial layer, the first sacrificial layer, and the mold layer using the first mask patterns, the second mask patterns, and the support structures as masks, removing the first mask patterns and second mask patterns, filling the storage node electrode holes with a conductive material and etching back the conductive material to expose the support structures, and removing the first sacrificial layer and the mold layer to form pillar-type storage node electrodes supported by the support structures.