Semiconductor Memory Pillar Width Variation for Etching Control
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Solution Overview
Problem
In semiconductor memory devices, increasing the number of word lines to enhance memory capacity poses challenges in controlling the position of the semiconductor channel body, particularly in reaching the source layer without the channel body becoming too thin, leading to potential occlusion and contact resistance issues.
Innovation Solution
The semiconductor memory device design includes a pillar layer with varying widths through different electrode and insulating layers, using an electrode layer as an etching stopper to improve depth controllability of memory holes and ensure the semiconductor layer reaches the source layer without thinning, thereby maintaining accurate end positions and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines is increased to enhance memory capacity, then the memory capacity is improved, but the controllability of the semiconductor channel body position deteriorates
Solution Approach 1:
The patent divides the channel body formation process into multiple stages: first forming a preliminary channel structure through word lines, then selectively removing insulating layers to create etching pathways, and finally forming the definitive channel body. This segmentation allows precise control of the channel body position even as the number of word lines increases.
Solution Approach 2:
The patent performs preliminary actions by forming insulating layers and preliminary channel structures before final channel body formation. The insulating layers are strategically placed and then selectively removed to guide the etching process, ensuring the channel body reaches the correct position regardless of the number of word lines.
2Length of moving object
If the semiconductor channel body is made thinner to reach the source layer, then the depth coverage is improved, but the contact resistance increases and occlusion occurs
Solution Approach 1:
The patent applies local quality by varying the width of the semiconductor channel body at different positions. The channel body is wider at the bottom near the source layer to ensure good electrical contact and avoid occlusion, and narrower at the top where it extends through word lines. This localized width variation maintains reliability while achieving the required depth.
Solution Approach 2:
The patent changes the width parameter of the channel body along its length. By controlling the etching process and using selective insulating layer removal, the channel body width is adjusted to be larger at the source layer interface, ensuring adequate contact area and preventing occlusion while maintaining the necessary depth to reach the source layer.
3Quantity of substance
If the number of electrode and insulating layers is increased, then the memory capacity is improved, but the etching depth controllability deteriorates
Solution Approach 1:
The patent uses insulating layers as intermediary elements that facilitate controlled etching. These insulating layers are formed between electrode layers and are selectively removed to create etching pathways. The insulating layers act as mediators that guide the etching process to the correct depth, enabling precise control even when the total number of electrode and insulating layers is large.
Solution Approach 2:
The patent segments the etching process by using selectively removable insulating layers at different depths. Each insulating layer can be removed independently to create staged etching pathways, allowing the etching depth to be controlled in increments rather than as a single deep etch, thereby maintaining precision even with many layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively avoids occlusion and enhances the accuracy of the semiconductor layer's end position, improving memory capacity and reducing contact resistance between the source layer and the semiconductor layer.
Implementation Method 1
using an electrode layer as an etching stopper to improve depth controllability of memory holes
Implementation Method 2
The pillar layer has conductivity, and includes a first portion extending through the first insulating layer and a second portion extending through the second electrode layer
Data Source
AI summary
A semiconductor memory device including a first electrode layer provided on a conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first insulating layer provided between the first electrode layer and the second electrode layer; and a pillar layer extending through the first electrode, the second electrode and the first insulating layer in a first direction directed from the conductive layer to the first electrode layer. The pillar layer includes a first portion extending through the first insulating layer and a second portion extending through the second electrode layer. The pillar layer has a first width in a second direction along a surface of the conductive layer at a periphery of the first portion, and a second width in the second direction at a periphery of the second portion. The second width is wider than the first width.