Pilot Signal Layout in Flash Memory Pages for Reliable Storage
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Solution Overview
Problem
Non-volatile memory devices face inefficiencies in data storage and retrieval due to fixed block and page sizes, leading to unused memory cells and inefficient erasure processes, particularly in NAND flash arrays, where data length often differs from physical page length.
Innovation Solution
A memory system that utilizes pilot cells and pilot data signals with multiple sequences of signal levels, allowing for flexible data distribution and encoding schemes like Reed Solomon and LDPC, to optimize memory cell usage and minimize disturbance parameters through pilot cell placement and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fixed block and page sizes are used in memory devices, then the memory structure is simple and easy to manage, but memory cells are wasted and storage efficiency decreases when data length differs from physical page length
Solution Approach 1:
The patent implements dynamic page sizing where the memory system can vary the number of memory cells per page based on data requirements. Different page lengths (e.g., 512, 1024, 2048 bytes) can be selected according to the actual data storage needs, allowing the system to adapt between fixed-structure simplicity and variable-structure efficiency.
Solution Approach 2:
The invention changes the parameter of page size from a fixed value to a variable value that can be adjusted according to data length requirements. The memory controller can select different page lengths and configure pilot cell positions dynamically, optimizing storage efficiency while maintaining manageable memory structures.
2Speed
If pilot cells are placed at fixed positions in memory pages, then the memory access pattern is simple and fast, but disturbance parameters increase due to repeated access to the same locations
Solution Approach 1:
The patent implements dynamic pilot cell positioning where the position of pilot cells varies across different pages or memory blocks. Instead of always placing pilot cells at the same locations, the system shifts or randomizes their positions to distribute wear and disturbance across different memory cell locations, reducing localized disturbance parameters while maintaining access efficiency.
Solution Approach 2:
The system performs preliminary placement of pilot cells at optimized positions before data writing operations. By pre-calculating and setting pilot cell locations that minimize disturbance to data cells, the system prepares the memory structure in advance to reduce interference and improve data reliability without impacting access speed.
3Reliability
If entire blocks or pages are erased in NAND flash memory, then the erasure process is simple and reliable, but time is wasted erasing unused memory cells when data length is shorter than page length
Solution Approach 1:
The patent segments the memory block into multiple variable-sized pages with different lengths. Instead of erasing entire blocks or fixed-size pages, the system can erase only the specific pages or portions of pages that contain valid data. This segmentation allows selective erasure of used memory regions while preserving unused cells, reducing erasure time while maintaining reliability through targeted error correction on actual data regions.
Data Source
AI summary
A memory system includes a memory having a plurality of cells. To perform a writing operation to store user data among the plurality of cells, the memory system further includes a pilot generator module, a multiplexer module, and a write module. The pilot generator module is configured to select between first and second schemes by which pilot data is to be stored, along with the user data, among the plurality of cells. The second scheme is different from the first scheme, and the pilot data includes a known predetermined sequence. The multiplexer module is configured to combine the pilot data and the user data in accordance with the selection of the first scheme and the second scheme. The write module is configured to write the pilot data and the user data, as combined by the multiplexer module, among the plurality of cells.