PIM Address Mapping with Frame Striping to Reduce Row Conflicts
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Solution Overview
Problem
Existing memory systems face significant row-conflicts due to rigid timing requirements and energy inefficiencies in accessing data elements from DRAM banks, particularly when performing operations involving operands from different pages, which impede processing-in-memory (PIM) efficiency.
Innovation Solution
Implementing hardware-software collaborative address mapping schemes, such as intra-bank frame striping (IBFS) and intra-channel frame striping (ICFS), to interleave data elements from consecutive frames within the same bank or channel, reducing the number of row activations and conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data elements from different pages are accessed using conventional address mapping, then memory operations can be performed, but row-conflicts occur frequently causing significant access latency and energy consumption
Solution Approach 1:
The patent segments the memory address space by separating frame identification bits from row address bits. This allows the memory controller to identify which frames are being accessed and selectively activate only the necessary rows, preventing row-conflicts by ensuring that data elements from different frames are mapped to different physical rows even when they belong to the same bank.
Solution Approach 2:
The patent introduces a new dimension in address mapping by utilizing frame bits (typically unused or lightly used bits) to control row activation decisions. Instead of relying solely on conventional row address bits, the system uses frame identification information to make intelligent row activation decisions, effectively adding a temporal/dimensional layer to the address mapping process that eliminates row-conflicts without sacrificing memory capacity.
2Productivity
If data elements from different pages are accessed using conventional address mapping, then memory operations can be performed, but excessive energy is consumed due to frequent row activations and pre-charges
Solution Approach 1:
The patent segments the memory address space by separating frame identification bits from row address bits. This allows the memory controller to identify which frames are being accessed and selectively activate only the necessary rows, preventing row-conflicts by ensuring that data elements from different frames are mapped to different physical rows even when they belong to the same bank.
Solution Approach 2:
The patent converts the typically wasted or lightly used frame bits into a beneficial resource for controlling row activation. By repurposing these frame identification bits to prevent row-conflicts, the system transforms what would be redundant information into a powerful mechanism for energy-efficient memory access, eliminating unnecessary row activations and their associated energy consumption.
3Speed
If naive interleaving is used to achieve memory level parallelism, then data from same page can be accessed in parallel, but row-conflicts occur when accessing operands from different pages
Solution Approach 1:
The patent implements dynamic row activation control based on frame identification. Instead of using static interleaving patterns that may cause conflicts, the system dynamically decides which rows to activate by examining the frame bits of the incoming memory requests. This allows the memory controller to adaptively prevent row-conflicts while maintaining parallelism, as it can selectively activate rows only when necessary and avoid activating rows that would cause conflicts with other simultaneous operations.
Solution Approach 2:
The patent uses frame identification information as feedback to control row activation decisions. By continuously monitoring which frames are being accessed and using this information to make real-time decisions about row activation, the system can prevent row-conflicts before they occur. This feedback mechanism allows the memory controller to coordinate multiple parallel access operations without causing conflicts, thereby maintaining high-speed operation.
Data Source
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AI summary
Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achieve higher performance by reducing row conflicts. Using an intra-bank frame striping policy (IBFS), corresponding subsets of data elements are interleaved into a single row of a bank. Using an intra-channel frame striping policy (ICFS), corresponding subsets of data elements are interleaved into a single channel row of a channel. A memory controller utilizes ICFS and/or IBFS to efficiently store and access data elements in memory, such as processing-in-memory (PIM) enabled memory.