Processing-in-Memory Arrays With RAS Timing Coordination
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face inefficiencies in processing performance and power consumption due to the need for external communication between processing resources and memory arrays, which can be addressed by integrating processing capabilities directly within the memory device.
Innovation Solution
Implementing a Processing-in-Memory (PIM) capable device that performs logical operations directly on data stored in memory arrays using sensing circuitry and a row address strobe component, coordinated by a RAS manager, allowing for in-memory operations without external data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is accessed via external bus between processing resources and memory array, then processing resources can execute instructions on data, but processing time and power consumption increase due to external communication overhead
Solution Approach 1:
The patent merges the processing resource and memory array into a single integrated device, allowing processing circuits to be located within the memory device. This eliminates external bus communication overhead and enables direct processing of data stored in the memory array, thereby reducing processing time while maintaining processing performance.
Solution Approach 2:
The patent introduces an intermediary processing circuit within the memory device that acts as a mediator between the external processing resource and the memory array. This intermediary can perform preliminary processing operations directly on data in the memory array, reducing the amount of data that needs to be transferred externally and thereby reducing overall processing time.
2Productivity
If data is accessed via external bus between processing resources and memory array, then processing resources can execute instructions on data, but power consumption increases due to external communication
Solution Approach 1:
The patent merges the processing resource and memory array into a single integrated device, allowing processing circuits to be located within the memory device. This eliminates external bus communication overhead and enables direct processing of data stored in the memory array, thereby reducing power consumption while maintaining processing performance.
Solution Approach 2:
The patent introduces an intermediary processing circuit within the memory device that acts as a mediator between the external processing resource and the memory array. This intermediary can perform preliminary processing operations directly on data in the memory array, reducing the amount of data that needs to be transferred externally and thereby reducing overall power consumption.
3Productivity
If processing resource is implemented external to memory array, then data can be accessed via bus, but bandwidth requirements for external communication increase
Solution Approach 1:
The patent merges the processing resource and memory array into a single integrated device, allowing processing circuits to be located within the memory device. This eliminates external bus communication overhead and enables direct processing of data stored in the memory array, thereby reducing bandwidth requirements for external communication while maintaining computational performance.
Data Source
AI summary
An example apparatus includes a processing in memory (PIM) capable device having an array of memory cells and sensing circuitry coupled to the array. The PIM capable includes a row address strobe (RAS) component selectably coupled to the array. The RAS component is configured to select, retrieve a data value from, and input a data value to a specific row in the array. The PIM capable device also includes a RAS manager selectably coupled to the RAS component. The RAS manager is configured to coordinate timing of a sequence of compute sub-operations performed using the RAS component. The apparatus also includes a source external to the PIM capable device. The RAS manager is configured to receive instructions from the source to control timing of performance of a compute operation using the sensing circuitry.