PIM Device Bias Data Feedback for Deterministic Arithmetic

The patent merges the processor and memory into a single integrated PIM device, where the arithmetic circuit is directly coupled to the memory cell array. This integration eliminates the need for separate data communication channels between processor and memory, thereby removing the communication bottleneck that limited AI application performance in traditional systems.

The PIM device performs arithmetic operations directly within the memory structure itself. The arithmetic circuit is integrated with the memory cell array, allowing data to be processed in-place without being transferred to a separate processor. This self-service capability enables the system to handle exponentially increasing computational demands by performing computations where the data resides, thereby maintaining high data processing speed even as neural network complexity increases.

The patent integrates the arithmetic circuit directly with the memory cell array in a unified PIM device structure. The arithmetic circuit includes components such as bit line circuits, word line circuits, and computation units that are physically and functionally coupled to the memory cells, enabling data to be read, processed, and written back without external data movement.

The PIM device is segmented into distinct functional units including memory cell arrays, arithmetic circuits, and control logic units. Each segment performs a specific function - the memory cells store data, the arithmetic circuits perform computations on the stored data, and the control logic coordinates operations. This segmentation allows the complex integrated structure to be managed through modular design, where each component can be optimized independently while working together to achieve high data processing speed.