In-Situ PIM Bootstrapping for Low-Latency Fully Homomorphic Encryption

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Solution Overview

Problem

Existing fully homomorphic encryption (FHE) systems face significant performance and memory overheads due to large data size expansion and computational costs, with bootstrapping being a major bottleneck, and current CPU and GPU implementations do not provide sufficient speedup for practical applications.

Innovation Solution

Implementing a fully homomorphic encryption system using in-situ processing-in-memory (PIM) with a server PIM accelerator for operations on encrypted data, employing pipelined architectures for bootstrapping and key switching, and utilizing PIM-enabled bootstrapping to maintain low noise levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If bootstrapping is used to reduce noise growth during FHE function evaluation, then more complex operations can be performed, but latency increases by 100-1000×

Engineering Contradiction:
Improvecomplexity of function evaluationVSAvoidlatency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The bootstrapping process is divided into multiple pipeline stages that can execute simultaneously. The system segments the bootstrapping operation into distinct computational steps that are distributed across multiple processing units, allowing parallel execution and reducing overall latency while maintaining the ability to perform complex FHE operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system implements dynamic pipeline scheduling that adapts to different FHE operation requirements. The pipeline can dynamically adjust its execution flow and resource allocation based on the specific bootstrapping needs, optimizing performance for varying levels of operational complexity without requiring full pipeline reconfiguration.

Inventive Principle:
Principle #15Dynamics

2Reliability

If FHE encryption is applied to preserve data privacy, then data security is enhanced, but data size expands from 4B to more than 20 KB

Engineering Contradiction:
Improvedata securityVSAvoiddata size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The system merges multiple FHE ciphertext operations into single pipeline executions. By combining related FHE operations and processing them together through the unified pipeline architecture, the system reduces redundant data expansion and memory operations, thereby mitigating the data size overhead while preserving security.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The FHE pipeline is designed as a universal processing architecture that can handle multiple types of FHE operations (encryption, decryption, bootstrapping, key switching) through a single unified system. This multi-functionality reduces the need for separate specialized hardware for each operation, optimizing resource utilization and reducing overall system overhead.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If homomorphic multiplication of FHE encrypted integers is performed, then computational capability is maintained, but tens of millions of operations are required

Engineering Contradiction:
Improvecomputational capabilityVSAvoidnumber of operations
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system performs preliminary preparation of FHE operands and pre-computation of intermediate values before the main multiplication operation. By pre-processing inputs and setting up computational intermediates in advance, the system reduces the number of operations required during the actual homomorphic multiplication, thereby maintaining computational capability while reducing operational complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The FHE pipeline maintains continuous execution of useful computational actions without idle cycles. The pipeline architecture ensures that processing units remain continuously engaged in productive FHE operations, eliminating wasted computation and reducing the total number of operations needed to complete homomorphic multiplication tasks.

Inventive Principle:
Principle #20Continuity of useful action

4Speed

If CPU and GPU implementations of RGSW-based FHE schemes are used, then processing speed is improved, but scaling is insufficient to provide adequate speedup

Engineering Contradiction:
Improveprocessing speedVSAvoidscaling capability
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The system transitions from traditional CPU/GPU processing dimensions to a memory-centric processing dimension with PIM. By organizing FHE operations around memory architecture rather than processor architecture, the system achieves scaling in a new dimension that overcomes the limitations of conventional processors, providing both speed improvement and enhanced scalability through memory bandwidth utilization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12500732B2Methods of operating on data in a fully homomorphic encryption system using in-situ processing-in-memory and related circuits
Publication Date: 2025.12.16 RGT UNIV OF CALIFORNIA
  • US12500732B2 patent drawing
  • US12500732B2 patent drawing
  • US12500732B2 patent drawing

AI summary

A method of operating on encrypted data can be performed by receiving ciphertexts at a server that is configured to operate on the ciphertexts generated using a 3rd generation RGSW based fully homomorphic encryption system, operating on the ciphertexts received at the server in response to requested operations to generate respective input ciphertexts including ciphertext polynomials and ciphertext integers that are representative of the input ciphertexts, and processing the input ciphertexts in a server processing-in-memory device, that is operatively coupled to the server, to perform operations on the input ciphertext using the server processing-in-memory device, in-situ.