PIM Device Column Control Circuit for Deterministic MAC Operations
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Solution Overview
Problem
Current processing-in-memory (PIM) devices face limitations in performing deterministic arithmetic operations efficiently due to the separation of processors and memory, leading to degraded performance in artificial intelligence applications, particularly in deep learning processes where increased computational demands are exponential and data communication between memory and processors is limited.
Innovation Solution
A PIM device is designed with integrated memory and processor capabilities, featuring a configuration that includes multiple memory banks and MAC operators, along with a column control circuit and global buffer, enabling deterministic MAC arithmetic operations by generating specific control signals for data access and processing, ensuring predictable and fixed latency in operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a general hardware system with separated memory and processor is used, then the system structure is simple, but the data communication between memory and processor is limited and performance is degraded
Solution Approach 1:
The patent merges memory and processor functions into a single integrated device. The PIM device includes memory cells for data storage and MAC operators for arithmetic operations within the same semiconductor chip, eliminating the need for separate memory and processor components. This integration enables direct arithmetic operations on stored data, dramatically improving data processing speed and computational efficiency for AI applications.
2Productivity
If the number of layers in neural network is increased to improve AI performance, then the computational performance improves, but the amount of computations required increases exponentially
Solution Approach 1:
The PIM device enables memory to perform arithmetic operations autonomously without requiring external processor intervention. The MAC operators are directly integrated with memory cells, allowing the memory system to self-service by performing multiplication and accumulation operations on data stored within its own structure. This eliminates data transfer overhead and reduces computation time for deep neural networks with multiple layers.
3Speed
If arithmetic operations are performed directly in the PIM device, then the data processing speed improves, but the control signal generation complexity increases
Solution Approach 1:
The column control circuit is designed as a multi-functional unit that generates multiple types of control signals (memory read control signals, buffer write control signals, memory write control signals, buffer read control signals) from a unified set of input signals (copy read signals, copy write signals, address signals). This universal control approach simplifies the overall control architecture while enabling direct arithmetic operations at high speed within the PIM device.
Data Source
AI summary
A PIM device includes a plurality of first storage regions, a second storage region, and a column control circuit. The second storage region is coupled to each of the plurality of first storage regions through a data transmission line. The column control circuit generates a memory read control signal for reading data stored in an initially selected storage region of the plurality of first storage regions and a buffer write control signal for writing the data read from the initially selected storage region to the second storage region. The column control circuit generates a global buffer read control signal for reading the data written to the second storage region and a memory write control signal for writing the data read from the second storage region to a subsequently selected storage region of the plurality of first storage regions.