PIM Controller Segmentation for AI Model Execution

The patent merges the PIM controller with the memory controller into a single integrated unit. This integration eliminates the need for separate communication interfaces and control logic, thereby reducing communication overhead and energy consumption while maintaining accelerated AI model execution through PIM operations.

The integrated controller performs multiple functions: it manages both standard memory operations and PIM-specific operations, classifies different operation types (PIM operations versus NLF operations), and generates appropriate control signals. This multi-functionality reduces the need for separate dedicated controllers, minimizing communication overhead.

The patent segments operations into two categories: PIM operations that can be executed directly in the memory device, and NLF (non-linear function) operations that require the host processor. This segmentation allows the PIM to handle straightforward computational tasks locally, improving host processor throughput without requiring the PIM to accommodate all possible operation types, thus controlling PIM area requirements.

The integrated memory controller acts as an intermediary that classifies incoming operations and routes them appropriately. It identifies which operations can be performed in PIM and which require NLF processing by the host processor, enabling efficient task distribution without overloading the PIM with operations it cannot efficiently handle, thereby optimizing the balance between productivity and PIM area.