Processing In Memory Device Reducing Data Transfer Latency
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Solution Overview
Problem
Memory bandwidth and latency issues in processing systems with stacked memory devices lead to inefficiencies and increased power consumption due to inter-device data communication penalties during multiple accesses.
Innovation Solution
A memory device and processing in memory (PIM) method that performs data-intensive operations like matrix multiplications by rearranging data and using read-write circuits to reduce data transfer between the memory device and external devices, enabling parallel bitwise multiplications and additions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked memory devices are used to increase memory capacity, then memory capacity is improved, but inter-device bandwidth and latency penalties increase due to data communication between stacked semiconductor dies
Solution Approach 1:
The patent combines memory storage and processing functions into a single memory device by integrating a processing circuit within the memory device structure. This merging eliminates the need for separate data transfer between memory and processor, thereby resolving the bandwidth and latency penalties associated with stacked memory devices while maintaining high memory capacity.
Solution Approach 2:
The memory device is designed with multi-functionality, serving both as storage medium and processing unit. The processing circuit within the memory device can perform computational operations directly on stored data, allowing the system to achieve both high capacity and high processing efficiency without the traditional memory-wall bottleneck.
2Quantity of substance
If stacked memory devices are used to increase memory capacity, then memory capacity is improved, but power consumption increases due to inter-device data communication
Solution Approach 1:
By merging storage and processing functions within the same memory device, the patent eliminates energy-consuming data transfer operations between stacked dies and external processors. The processing circuit operates directly on data within the memory array, significantly reducing power consumption while maintaining high capacity through the stacked architecture.
3Adaptability or versatility
If multiple accesses are required for tasks requiring multiple accesses to stacked memory device, then data communication between stacked semiconductor dies increases, but processing time increases due to inter-device bandwidth and latency penalties
Solution Approach 1:
The integration of processing circuitry within the memory device allows multiple data accesses and processing operations to occur within a single device without incurring inter-device communication delays. This merging enables flexible multi-access operations while eliminating the time penalties associated with data transfer between stacked dies.
Data Source
AI summary
In a processing in memory (PIM) method using a memory device, m*n multiplicand arrangement bits are stored in m*n memory cells by copying and arranging m multiplicand bits of a multiplicand value and m*n multiplier arrangement bits are stored in m*n read-write unit circuits corresponding to the m*n memory cells by copying and arranging n multiplier bits of a multiplier value. The m*n multiplicand arrangement bits stored in the m*n memory cells are selectively read based on the m*n multiplier arrangement bits stored in the m*n read-write unit circuits, and m*n multiplication bits are stored in the m*n read-write unit circuits based on the selectively read m*n multiplicand arrangement bits. A multiplication value of the multiplicand value and the multiplier value is determined based on the m*n multiplication bits stored in the m*n read-write unit circuits.