PIM Diode Resistance Change Memory 3D Integration
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Solution Overview
Problem
The challenge in developing resistance change memory technologies is the aspect ratio of the gap formed after processing the rectification element, which is disadvantageous for configuring a three-dimensional memory cell array, and existing solutions fail to efficiently address the need for high storage density and operational speed while maintaining effective rectification properties.
Innovation Solution
A resistance change memory design incorporating a pim diode as the non-ohmic element, composed of a metal layer, an intrinsic semiconductor layer, and a p-type semiconductor layer, which reduces the thickness and aspect ratio of the non-ohmic element, enabling efficient three-dimensional integration and improved rectification characteristics for both unipolar and bipolar operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of components of the rectification element is increased, then the rectification properties are improved, but the aspect ratio of the gap becomes higher which is disadvantageous for three-dimensional integration
Solution Approach 1:
The patent changes the structural parameters of the rectification element by introducing a multi-layer configuration (first rectification element, second rectification element, and cap layer) with progressively decreasing thicknesses. This parameter optimization allows achieving adequate rectification properties while reducing the overall thickness to 50nm or less, thereby lowering the aspect ratio for three-dimensional integration.
Solution Approach 2:
The patent employs composite material structure by stacking multiple rectification element layers (first rectification element 24a, second rectification element 24b) with different material compositions and thicknesses, along with a cap layer 24c. This composite approach enables optimization of both rectification performance and dimensional characteristics for 3D compatibility.
2Shape
If the thickness of the non-ohmic element is reduced for three-dimensional integration, then the aspect ratio is improved, but the rectification properties may be compromised
Solution Approach 1:
The patent segments the rectification function across multiple thin layers instead of using a single thick layer. The first rectification element 24a, second rectification element 24b, and cap layer 24c are stacked in sequence, each contributing to the overall rectification performance while maintaining individual thicknesses that enable low aspect ratio and three-dimensional integration.
3Ease of manufacture
If a conventional rectification element structure is used, then the manufacturing process is simpler, but the storage density and operational efficiency are insufficient
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking by implementing multiple rectification element layers stacked in the thickness direction. This dimensional change enables significantly higher storage density within the same footprint area while maintaining compatibility with standard semiconductor manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The pim diode-based design enhances the storage density of the cross-point type memory cell array, maintains effective rectification properties, and supports both unipolar and bipolar operations, overcoming the limitations of aspect ratio and operational efficiency in existing technologies.
Implementation Method 1
a first non-ohmic element having a first diode characteristic and connected in series with the memory element between the bit line and the word line, and a second non-ohmic element having a second diode characteristic and connected in series with the memory element between the bit line and the word line
Implementation Method 2
a memory element and a rectification element that are connected in series between a word line and a bit line
Data Source
AI summary
According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The memory element stores data in accordance with a change in a resistance state. The non-ohmic element includes a metal layer, a first semiconductor layer containing a first impurity, and a second semiconductor layer which is provided between the first semiconductor layer and the metal layer and which has an unevenly distributed layer.