PIM ECC-Space Operations for In-Memory Error-Corrected Data Processing

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Solution Overview

Problem

ECC decoding and encoding processes in CPUs add significant operation overhead, reducing the speed performance of data manipulation in memory devices, especially when processing ECC encoded data.

Innovation Solution

Implementing a PIM architecture with ECC-Space operations that allow direct manipulation of ECC encoded data within the memory device, using truncated ECC-Space operations and ECC-Space operations to generate new ECC encoded data without the need for decoding, thereby improving data manipulation speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ECC decoding processes are performed in CPU, then data errors can be corrected, but operation overhead increases and data manipulation speed decreases

Engineering Contradiction:
Improvedata error correction capabilityVSAvoiddata manipulation speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the ECC processing function from the CPU to dedicated logic circuits within the memory device. The ECC decoding function is separated into independent hardware modules (syndrome calculation unit, error correction unit) that operate parallel to the main processing logic, allowing simultaneous data manipulation and error correction without CPU intervention.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary ECC processing unit within the memory device that acts as a mediator between stored ECC-encoded data and the CPU. This intermediary unit performs decoding and error correction locally, translating ECC-encoded data into usable form without requiring CPU-based decoding operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If ECC encoding processes are performed in CPU, then data can be protected against corruption, but operation overhead increases and processing efficiency decreases

Engineering Contradiction:
Improvedata protection capabilityVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the ECC encoding function from CPU operations into dedicated encoding logic circuits within the memory device. These circuits perform encoding operations independently during data write operations, separating the protection function from general-purpose CPU processing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs ECC encoding in advance during the data write operation before data is stored. The encoding is completed as part of the write process, so that when data is read, it is already protected and ready for use without requiring additional CPU-based encoding operations.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If ECC encoded data are decoded before processing, then processing can be performed on original data, but additional decoding overhead reduces overall system performance

Engineering Contradiction:
Improveprocessing capability on original dataVSAvoiddecoding overhead time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent enables the memory device to perform self-service ECC decoding through integrated logic circuits that automatically decode ECC-encoded data during read operations. This self-service capability eliminates the need for external CPU-based decoding, allowing the memory device to handle its own error correction independently.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent merges the ECC decoding function with the memory device's read operation logic. The decoding process is combined with the data retrieval operation itself, so that decoding occurs in parallel with or as part of the normal read sequence rather than as a separate sequential step.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11687412B2Processing-in-memory instruction set with homomorphic error correction
Publication Date: 2023.06.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11687412B2 patent drawing
  • US11687412B2 patent drawing
  • US11687412B2 patent drawing

AI summary

A method includes generating an ECC encoded output data by executing an ECC-Space operation using an ECC encoded first data from a memory as a first operand and an ECC encoded second data from the memory as a second operand. The ECC-Space operation is translated from a two operands operation that is operative to transform a first data and a second data into a third data. A result of encoding the first data is the ECC encoded first data and a result of encoding the second data is the ECC encoded second data if the first data and the second data are encoded with an ECC algorithm. The method also includes storing the ECC encoded output data to the memory. The ECC encoded output data is identical to a result of encoding the third data if the third data is encoded with the ECC algorithm.