PiM Error Logging and Selective Reset for Debug Recovery

The patent segments the PiM device into distinct functional blocks: memory array, PiM logic, status register, command history register, and debug interface. This segmentation allows selective resetting of only the PiM logic block when an error occurs, rather than resetting the entire DRAM array. The status register and command history register capture error information at the block level, enabling targeted recovery that preserves data in the memory array while restoring only the faulty logic component.

The patent implements preliminary error detection and logging mechanisms before full system failure occurs. Status registers and command history registers continuously monitor and record PiM operations, detecting errors early in the execution sequence. This preliminary detection allows the system to log the specific command that caused the error and reset only the PiM logic block, preventing cascading failures that would require a complete array reset and cause total data loss.

The patent segments the reset operation to affect only the PiM logic block rather than the entire DRAM array. This segmented approach reduces reset latency significantly because only the computational logic needs to be reinitialized, not the entire memory structure. The status register and command history register provide fast error identification at the block level, enabling rapid targeted recovery that minimizes time loss while maintaining system reliability.

The patent implements a feedback mechanism where the status register and command history register continuously report PiM operation status to the host system. When an error is detected, this feedback loop provides immediate information about the error type and location, enabling the host to initiate a targeted PiM logic reset rather than a conservative full array reset. This feedback-driven approach reduces latency by eliminating unnecessary reset operations on healthy memory portions.

The patent merges error detection and logging functionality directly into the existing PiM architecture blocks. The status register and command history register are integrated with the PiM logic block, sharing control signals and data pathways. This merging approach enables comprehensive error detection without adding separate complex monitoring systems, as the existing register structures are repurposed to serve both normal operation and error detection functions.

The status register and command history register serve multiple functions: they track normal PiM operation status, log error conditions, and provide debugging information to the host system. This multi-functionality reduces the need for dedicated error detection hardware, as existing universal register structures handle both operational monitoring and error detection tasks, thereby limiting the increase in device complexity while improving reliability.

The patent merges command logging functionality with the existing status register infrastructure. The command history register uses the same control and data pathways as normal PiM operations, combining debugging capabilities with operational monitoring. This merging allows comprehensive command logging without duplicating existing register structures, thereby improving debug capability while limiting the increase in device complexity.

The command history register creates a simplified copy of the command sequence executed by the PiM logic block. Rather than implementing complex tracing mechanisms, the system copies essential command information into the status register structure, which can then be read by the host system for debugging. This copying approach provides adequate debug capability using existing register hardware, avoiding the need for more complex logging infrastructure.