PIM System ID-Channel Mapper for Neural Network Speed
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Solution Overview
Problem
Current processing-in-memory (PIM) systems face limitations in performance due to the separation of processors and memory, leading to degraded AI performance, particularly in deep learning applications, where increased computational demands and data communication constraints hinder efficient neural network operations.
Innovation Solution
A PIM system is designed with an ID-channel mapper and multiple PIM controllers, where PIM devices are coupled through channels, enabling deterministic arithmetic operations by integrating processors and memory within a semiconductor chip, allowing for improved data processing speed in neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a general hardware system with separated memory and processor is used, then device complexity is reduced and ease of manufacture is improved, but data processing speed and AI performance are degraded due to data communication limitations
Solution Approach 1:
The patent merges the processor and memory into a single integrated PIM device, eliminating the need for separate components and their interconnection. This integration allows arithmetic operations to be performed directly within the memory device, dramatically improving data processing speed by eliminating data transfer delays between separate memory and processor units.
2Measurement precision
If the number of neural network layers is increased to improve AI performance, then computational accuracy is improved, but the amount of computation required and data communication demands increase exponentially
Solution Approach 1:
By integrating multiple PIM devices with dedicated arithmetic circuits within a single memory chip, the system achieves high computational throughput required for deep learning. The integration allows multiple layers of neural networks to be processed with reduced data communication overhead, as data can be accessed and processed within the same device without external memory accesses.
3Speed
If PIM devices are integrated with processors in one semiconductor chip, then data processing speed is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent combines memory cells and arithmetic circuits into a single PIM device structure that can be manufactured using standard semiconductor fabrication processes. This integration is achieved through careful architectural design where the arithmetic units are directly coupled to memory banks within the same chip, enabling high-speed processing while maintaining compatibility with existing manufacturing techniques.
Data Source
AI summary
A processing-in-memory (PIM) system includes a host including an identification (ID)-channel mapper configured to generate a channel address corresponding to an identification received from outside the PIM system, and a plurality of PIM controllers coupled to the host through a plurality of channels, and the plurality of PIM devices coupled to the plurality of PIM controllers through the plurality of channels.