PIM Memory Device with Indirect Address Generation
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Solution Overview
Problem
Existing processing-in-memory (PIM) devices face limitations in addressing memory bottlenecks due to the need for direct addressing mode, which is inflexible and inefficient for large-capacity data structures used in machine learning and natural language processing, leading to reduced system performance.
Innovation Solution
A PIM memory device and method that enables indirect addressing by using a processing-in-memory control unit to generate effective addresses through a base register and offset values, allowing dynamic memory access for data structures like graphs and arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If direct addressing mode is used in PIM devices, then memory access is simple and fast, but flexibility for large-capacity data structures is lost
Solution Approach 1:
The patent implements dynamic addressing mode selection capability in the PIM device, allowing the system to switch between direct addressing mode (for speed) and indirect addressing mode (for flexibility) based on the specific operation requirements. This is achieved through control logic that determines the appropriate addressing mode and configures the address generation circuit accordingly, resolving the contradiction between fixed-speed direct addressing and flexible indirect addressing.
2Adaptability or versatility
If indirect addressing mode is added to PIM devices, then flexibility for data structures is improved, but device complexity increases
Solution Approach 1:
The patent designs a universal address generation unit that can perform both direct addressing and indirect addressing functions. The same hardware block is configured differently based on control signals, rather than having separate dedicated circuits for each addressing mode. This multi-functional design provides indirect addressing capability while minimizing the increase in device complexity.
Solution Approach 2:
The patent changes the operational parameters of the address generation circuit based on the required addressing mode. By modifying control parameters (such as enabling/disabling register read operations, selecting different data paths), the system transitions between direct and indirect addressing without requiring fundamentally different hardware structures, thus limiting complexity increase.
3Adaptability or versatility
If indirect addressing is implemented in PIM, then support for large-capacity data structures is improved, but data transmission needs increase
Solution Approach 1:
The patent segments the address generation process into multiple components: base address from control registers, offset values from instruction fields or additional registers, and a combination unit that merges them. This segmentation allows efficient handling of indirect addressing by breaking down the address formation into manageable parts, reducing the overall data transmission burden while maintaining support for large-capacity data structures.
Data Source
AI summary
An embodiment of the present invention provides a processing-in-memory memory device comprising: a memory bank including a memory array for receiving a memory request from a memory controller, and a PIM engine for executing processing-in-memory according to the PIM instruction; and a processing-in-memory (PIM) control unit for controlling the processing-in-memory of the PIM engine by identifying a PIM instruction corresponding to the memory request, and storing addressing mode selection information for selecting one among an indirect address and a direct address according to the identified PIM instruction, wherein when the indirect address is used, the PIM control unit uses a register value of the processing-in-memory control unit as a base register value, reads an immediate value in the PIM instruction, a register value of the PIM engine, or an offset value of the memory bank, and generates an effective address for the processing-in-memory in an indirect addressing mode.