In-Memory Interconnect Protocol Registers in PIM Nodes
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Solution Overview
Problem
Current computer systems require dedicated SRAM memory regions for interconnect protocol configuration registers, which reduces the available space for processor or memory regions and limits the scalability of complex configuration data storage.
Innovation Solution
Allocating interconnect protocol configuration registers in cacheable regions of memory, specifically in Processing-in-Memory (PIM) nodes with 3D stacked memory, allowing these registers to be stored in memory rather than dedicated hardware, and utilizing cache coherence to ensure fast access and reduce physical footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated SRAM memory regions are used for interconnect protocol configuration registers, then reliable storage and fast access to configuration data is ensured, but the available space for processor or memory regions is reduced
Solution Approach 1:
The patent merges the previously separate configuration register storage (dedicated SRAM) with the main memory system. Configuration registers are allocated within the DRAM memory space and accessed through the memory interface, eliminating the need for separate dedicated register hardware and freeing up logic die space.
Solution Approach 2:
The DRAM memory system is given multiple functions: it serves both as the main memory for data storage and as the storage medium for interconnect protocol configuration registers. This universal usage eliminates dedicated hardware for configuration registers while maintaining reliable access through the memory controller and cache coherence mechanisms.
2Adaptability or versatility
If larger register spaces are allocated for complex configuration data, then support for advanced memory and interconnect features is improved, but the physical footprint of the interconnect protocol increases
Solution Approach 1:
The patent transitions from a two-dimensional layout where configuration registers occupied horizontal space on the logic die to a vertical arrangement where configuration data is stored in the third dimension of DRAM memory space. This allows exponentially larger register spaces without increasing the physical footprint of the interconnect protocol hardware.
Solution Approach 2:
Instead of duplicating physical register hardware for each configuration parameter, the system uses memory addresses to represent configuration registers. The memory controller and cache coherence protocol create virtual copies of the register access interface, allowing large configuration spaces to be addressed through software without requiring proportional physical hardware resources.
3Area of stationary object
If configuration registers are moved to memory, then physical footprint is reduced, but access time may increase due to memory latency
Solution Approach 1:
The system performs preliminary actions by caching configuration register data in the cache memory hierarchy before it is needed for processing. The cache coherence protocol ensures that frequently accessed configuration data is pre-loaded into faster cache memory layers, reducing the effective access time despite the physical location in DRAM.
Solution Approach 2:
The patent implements dynamic access patterns where frequently accessed configuration registers are cached in faster memory layers (SRAM cache) while less frequently accessed data remains in DRAM. The cache coherence mechanism dynamically manages this hierarchy, providing fast access times for critical configuration data while maintaining the benefit of reduced physical footprint.
Data Source
AI summary
Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.