PIM Interface Circuit Command Decoding for Hardware Complexity Reduction
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Solution Overview
Problem
Current semiconductor memory devices face complexity and increased costs due to the need for separate interfaces and additional hardware configurations to support internal processing operations, which complicates hardware implementations and increases costs.
Innovation Solution
A memory device with a processor in memory (PIM) circuit and an interface circuit that decodes commands and addresses to generate internal control signals, allowing the PIM circuit to operate in different modes based on voltage signals, thereby simplifying internal processing operations and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate interface for internal processing is used, then internal processing operations can be performed, but hardware configurations become complicated and costs increase
Solution Approach 1:
The interface circuit is designed to serve dual purposes: it handles both traditional memory operations and internal processing operations (PIM operations). By making the interface circuit universal, the patent eliminates the need for a separate dedicated interface for internal processing, thereby reducing hardware complexity while maintaining full functionality for both memory access and arithmetic operations
Solution Approach 2:
The patent combines the memory interface and the internal processing interface into a single unified interface circuit. This merging of functions allows the same physical interface to support both standard memory read/write operations and PIM arithmetic operations, reducing the overall number of components and simplifying hardware configuration
2Adaptability or versatility
If a separate interface for internal processing is used, then internal processing operations can be performed, but costs for supporting internal processing operations increase
Solution Approach 1:
By designing the interface circuit to be universal and support multiple functions (both memory operations and internal processing operations), the patent reduces the total component count required. This multi-functionality approach lowers manufacturing costs by eliminating redundant interface hardware that would otherwise be needed for dedicated internal processing support
3Adaptability or versatility
If multiple protocols are supported in the interface, then internal processing and normal operations can be performed through the same interface, but the interface circuit becomes more complex
Solution Approach 1:
The interface circuit employs dynamic protocol selection capability, allowing it to adaptively switch between different protocols (memory protocol and PIM protocol) based on the operation type. This dynamic behavior enables a single interface to handle multiple protocols without requiring separate dedicated circuits for each protocol, managing complexity through flexible control logic rather than hardware multiplication
Data Source
AI summary
A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.