PIM-Based Join Processing for DIMM-Compatible Data Acceleration
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Solution Overview
Problem
Existing computing systems face data bottlenecks and excessive power consumption due to the separation of memory and processor, and existing techniques for accelerating relational operations using PIM hardware are not compatible with the actual architecture of PIM-enabled DIMMs, necessitating a new join algorithm optimized for PIM-enabled DIMMs.
Innovation Solution
A PIM-based computing device that utilizes a PIM module with a memory processor to perform global partitioning of data sets, implementing a rotate-and-stream (RnS) and unordered scatter-gather (USG) operations to optimize communication between dual in-line memory modules, and supports join operations like hash join, sort-merge join, and nest-loop join, maximizing throughput and compatibility with DIMM architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between CPU and main memory using existing computing architecture, then data access is possible, but data bottleneck and excessive power consumption occur
Solution Approach 1:
The patent merges memory and processor operations by implementing PIM modules that perform join operations directly within the memory hierarchy. The PIM module combines storage functionality with computational capability, allowing data processing to occur where data resides, thereby eliminating the need for frequent data transfer between CPU and main memory and reducing associated power consumption.
Solution Approach 2:
The patent introduces a new dimensional approach by adding computational layers within the memory hierarchy itself. Instead of the traditional single-dimension data transfer path between CPU and memory, the system adds intermediate computational stages at the PIM module level, creating a multi-dimensional processing architecture that reduces transfer distances and energy consumption.
2Productivity
If PIM hardware simulators and existing acceleration techniques are used, then join operation acceleration is achieved, but compatibility with actual PIM-enabled DIMM architecture is lost
Solution Approach 1:
The patent applies local quality by designing PIM module-specific join algorithms that are optimized for the actual DIMM architecture's local characteristics. The global partitioning strategy and inter-IDP communication protocols are tailored to match the specific memory bank organization, channel structure, and address mapping of PIM-enabled DIMMs, ensuring both high performance and architectural compatibility.
Solution Approach 2:
The patent changes key architectural parameters including data partitioning strategies, communication protocols between IDPs, and memory access patterns to align with the actual PIM-enabled DIMM specification. By adjusting these parameters to match the target architecture's capabilities and constraints, the system achieves both acceleration and compatibility simultaneously.
3Ease of operation
If global partitioning is performed by CPU, then data distribution is achieved, but communication efficiency between IDPs is suboptimal
Solution Approach 1:
The patent introduces the PIM module as an intermediary that performs global partitioning operations locally within the memory subsystem. Instead of the CPU directly managing data distribution, the PIM module acts as an intermediate processor that handles partitioning and prepares data for efficient inter-IDP communication, reducing the communication overhead and improving overall system efficiency.
Data Source
AI summary
A processing-in-memory (PIM)-based computing device includes a main memory configured to store first and second data sets, a PIM module configured as an in-line memory module including a memory processor, a working memory, and a memory bank, the memory processor being connected to the working memory and performing a join operation on the first and second data sets loaded into the working memory, and a processor configured to form first and second channels with the main memory and the PIM module, import the first and second data sets through the first channel, and store the first and second data sets in the memory bank through the second channel.