Reconfigurable Processing-in-Memory Logic for Parallel Throughput
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Solution Overview
Problem
Existing computer systems face challenges in improving throughput while minimizing energy consumption and cost, as increasing processing cores leads to exorbitant costs and inefficiencies in parallel computation.
Innovation Solution
Implementing reconfigurable processing-in-memory (PIM) logic within memory devices equipped with logic arrays and control blocks, utilizing pull networks to control memory arrays and manage computations, enabling highly parallel computational pipelines without the need for extensive processing core expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processing cores is increased to improve throughput, then computational throughput is improved, but energy consumption and system cost increase exorbitantly
Solution Approach 1:
The patent merges memory storage and logic processing functions into a single integrated structure. Memory cells are equipped with logic arrays and control blocks that enable computations to be performed directly within the memory array, eliminating the need for separate processing cores and reducing energy consumption associated with data movement between memory and processor.
Solution Approach 2:
The memory device is designed with reconfigurable logic arrays that can perform multiple computational functions. The same memory infrastructure serves both as storage and as a programmable processing unit, allowing the system to handle various computational tasks without requiring additional specialized processing cores for each function.
2Productivity
If the number of processing cores is increased to improve throughput, then computational throughput is improved, but system cost increases exorbitantly
Solution Approach 1:
The patent merges memory storage and logic processing functions into a single integrated structure. Memory cells are equipped with logic arrays and control blocks that enable computations to be performed directly within the memory array, eliminating the need for separate processing cores and reducing energy consumption associated with data movement between memory and processor.
Solution Approach 2:
The memory device is designed with reconfigurable logic arrays that can perform multiple computational functions. The same memory infrastructure serves both as storage and as a programmable processing unit, allowing the system to handle various computational tasks without requiring additional specialized processing cores for each function.
3Productivity
If specialized processors are used to achieve high parallelism, then computational throughput is improved, but energy consumption increases
Solution Approach 1:
The patent merges memory storage and logic processing functions into a single integrated structure. Memory cells are equipped with logic arrays and control blocks that enable computations to be performed directly within the memory array, eliminating the need for separate processing cores and reducing energy consumption associated with data movement between memory and processor.
Data Source
AI summary
An example system implementing a processing-in-memory pipeline includes: a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; a logic array coupled to the memory array, the logic array to implement configurable logic controlling the plurality of memory cells; and a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of: one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines.