Processor-In-Memory Lookup Table for Instruction Retrieval
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Solution Overview
Problem
The von Neumann architecture leads to a bottleneck due to the inevitable delay caused by frequent data movements between separate processors and memory, limiting processor speed and throughput.
Innovation Solution
A processor-in-memory (PIM) system is introduced, which includes an internal processor, memory, and a register for storing instruction meta-information. The system generates a lookup table by predicting future instructions and stores it in memory, allowing for efficient retrieval and output of instructions via an external processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instructions are generated each time an operation is performed in the von Neumann architecture, then the processor can execute operations, but the frequent data movements between processor and memory cause delays that limit processor speed and throughput
Solution Approach 1:
The patent merges the processor and memory into a single integrated unit (processor-in-memory), eliminating the physical separation that causes data movement delays. The processor core is directly integrated with the memory array, allowing instructions to be generated and executed without external data transfers, thus resolving the throughput limitation caused by von Neumann bottleneck.
Solution Approach 2:
The patent implements a lookup table that pre-generates and stores instructions based on operation types before they are actually executed. When an operation needs to be performed, the corresponding pre-generated instruction is retrieved from the lookup table rather than being generated from scratch, reducing the time required for instruction preparation and improving overall processing speed.
2Speed
If a lookup table is generated by predicting future instructions, then instruction retrieval speed is improved, but the complexity of generating and maintaining the lookup table increases
Solution Approach 1:
The system implements self-service through automatic lookup table generation and maintenance. The processor-in-memory automatically predicts future instructions based on operation patterns and updates the lookup table without external intervention. This self-managing mechanism reduces the need for complex external control logic while maintaining high instruction retrieval speed.
Solution Approach 2:
The patent employs feedback mechanisms where the system monitors actual instruction execution patterns and uses this information to refine and update the lookup table predictions. By continuously learning from execution history and adjusting prediction accuracy, the system improves instruction retrieval speed while managing complexity through adaptive optimization rather than static complex structures.
Data Source
AI summary
A processor-in-memory (PIM) and a method of outputting an instruction using a PIM. The PIM includes an internal processor, a memory, and a register configured to store instruction meta information. The memory is configured to store a lookup table generated by predicting a future instruction. The external processor is configured to retrieve an instruction corresponding to the instruction meta information from the lookup table in response to a PIM application programming interface (API) call instruction including the instruction meta information. The instruction corresponding to the instruction meta information is output based on a retrieval result.