PIM MAC Operator Using FP-to-Fixed Accumulation for Deep Learning
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Solution Overview
Problem
Processing-in-memory (PIM) systems face limitations in deep learning applications due to the separation of memory and processor, leading to degraded performance from limited data communication between them, necessitating an integrated solution for improved neural network computation.
Innovation Solution
A PIM system with a MAC operator that includes multipliers for floating-point multiplication, floating-point-to-fixed-point converters, and an adder tree, configured to perform arithmetic operations efficiently by expanding the mantissa of the multiplication result data, enabling faster data processing within the memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory and processor are separated in a general hardware system, then the system structure is simple and easy to manufacture, but the performance of artificial intelligence is degraded due to limitation of data communication between memory and processor
Solution Approach 1:
The patent merges memory and processor functions into a single integrated device. The memory device includes memory cells for storage and MAC operators for arithmetic operations, eliminating the need for separate memory and processor components. This integration allows data to be processed directly within the memory device, removing communication bottlenecks while maintaining manufacturing simplicity through a unified semiconductor structure.
2Productivity
If the number of layers in neural network is increased to improve deep learning performance, then the computation capability is enhanced, but the amount of computation required increases exponentially
Solution Approach 1:
The MAC operator performs multiplication and accumulation operations directly within the memory device using the stored data itself, without requiring external processor intervention. The memory cells hold input data, weights, and partial products, and the MAC operator uses these stored values to compute results, enabling the system to serve its own computation needs internally and reducing the exponential growth of external computation requirements.
3Measurement precision
If floating-point format is used for multiplication operation, then the precision of calculation is improved, but the complexity of the multiplier circuit increases
Solution Approach 1:
The floating-point multiplication is segmented into distinct operational phases: exponent addition, mantissa multiplication, and result normalization. The MAC operator processes these segments sequentially, with each stage handling a specific aspect of the calculation. This segmentation allows the use of simpler circuitry for each individual stage while maintaining overall floating-point precision, rather than requiring a single complex multiplier circuit.
4Device complexity
If data communication between memory and processor is limited, then the hardware structure is simpler, but the data processing speed is degraded
Solution Approach 1:
The MAC operator acts as an intermediary component within the memory device that bridges the gap between stored data and computation results. It receives input data and weights from memory cells, performs arithmetic operations using these stored values, and directly writes results back to memory cells. This intermediary function eliminates the need for data to travel to and from external processors, maintaining simple hardware structure while dramatically improving data processing speed.
Data Source
AI summary
A MAC operator includes a plurality of multipliers configured to perform a multiplication operation on a floating-point format first data and a floating-point format second data to output a floating-point format multiplication result data, a plurality of floating-point-to-fixed-point converters configured to receive the floating-point format multiplication result data from each of the plurality of multipliers and convert into a fixed-point format multiplication result data to be output, and an adder tree configured to perform an addition operation on the fixed-point format multiplication result data that is output from the plurality of floating-point-to-fixed-point converters. If a first mantissa of the first data and a second mantissa of the second data are composed of ‘M’-bit (‘M’ being a natural number), each of the plurality of multipliers is configured to perform the multiplication operation so that the fixed-point format multiplication result data includes a mantissa of 2*(M+1) bits.


