PIM Memory Bank Layout for Faster Neural Network Access
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Solution Overview
Problem
The von Neumann structure's memory device and computation device separation leads to reduced computation speed due to data transfer time during large computations like artificial neural network operations.
Innovation Solution
A semiconductor memory device with a processing-in-memory (PIM) structure, featuring banks with varying memory cell array sizes and a processor adjacent to a smaller array, allowing for faster access and computation within the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a processing-in-memory structure is introduced to enable computations within the memory device, then computation speed is improved, but device size increases
Solution Approach 1:
The memory device is divided into multiple banks, each containing different sizes of memory cell arrays. This segmentation allows the processor to access smaller arrays faster while maintaining the option to access larger arrays when needed, thereby improving computation speed without requiring all banks to have maximum size which would increase overall device area.
Solution Approach 2:
Different banks are configured with different memory cell array sizes according to local computation needs. The processor is positioned adjacent to smaller memory cell arrays in specific banks to minimize access distance and maximize computation speed for frequently used data, while other banks maintain larger arrays for capacity requirements.
2Speed
If memory cell array size is reduced to improve access speed, then computation performance is improved, but storage capacity is reduced
Solution Approach 1:
The total storage capacity is segmented across multiple banks, each with its own memory cell array of optimized size. This allows the system to achieve fast access speeds by utilizing smaller arrays in banks adjacent to the processor while maintaining overall high storage capacity through the combined capacity of all banks.
Solution Approach 2:
Instead of increasing the size of a single memory cell array to improve capacity, the system adds more banks with varying array sizes. This dimensional expansion from single-array to multi-array architecture allows simultaneous optimization of both speed (through smaller arrays) and capacity (through multiple arrays).
Data Source
AI summary
At least one embodiment of the present disclosure provides a semiconductor memory device including: a substrate; a plurality of banks on the substrate, the plurality of banks including a first memory cell array of a first size and a second memory cell array of a second size, the second size being smaller than the first size; a peripheral circuit disposed between at least two of the plurality of banks; and a processor disposed adjacent to the second memory cell array.