PIM Memory Banks with Segmented Address Generation
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Solution Overview
Problem
The existing memory devices face a slowdown in arithmetic processing speed due to the need for the arithmetic processing device to acquire data from the memory device before performing operations, which can be mitigated by integrating processing-in-memory (PIM) capabilities within the memory device.
Innovation Solution
A memory device is designed with multiple banks and PIM blocks that can generate internal row addresses to access different rows of memory cells simultaneously, allowing for concurrent data processing and reducing the time required for read operations and improving power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is acquired sequentially from memory device before arithmetic operations, then data processing accuracy is ensured, but arithmetic processing speed deteriorates
Solution Approach 1:
The patent merges the memory device and arithmetic processing unit into a single integrated structure. The memory device includes multiple banks with corresponding PIM blocks that can perform arithmetic operations directly on stored data, eliminating the need to transfer data externally before processing. This integration allows simultaneous data storage and computation, resolving the speed-time contradiction.
Solution Approach 2:
The memory device is segmented into multiple independent banks, each with its own PIM block and address generating unit. This segmentation allows parallel access to different banks simultaneously, with each bank independently generating addresses and performing operations. The division into multiple operational units increases overall processing throughput while maintaining data accuracy.
2Productivity
If multiple banks are accessed simultaneously with independently generated addresses, then processing throughput is improved, but address management complexity increases
Solution Approach 1:
The address management system is segmented by allocating one address generating unit to each bank. Each address generating unit independently manages addresses for its corresponding bank, eliminating the need for a complex centralized address management system. This distributed address management simplifies control logic while enabling simultaneous access to multiple banks.
Solution Approach 2:
Each bank's address generating unit autonomously generates its own row and column addresses based on input data, without requiring external address coordination. The address generating units self-manage their respective banks' access patterns, reducing overall system complexity while maintaining high throughput through parallel independent operations.
Data Source
AI summary
A memory device includes a memory bank including a plurality of banks that comprise memory cells, and a PIM (processing in memory) circuit including a plurality of PIM blocks, each of the PIM blocks including an arithmetic logic unit (ALU) configured to perform an arithmetic operation using internal data acquired from at least one of the plurality of banks or an address generating unit. The plurality of PIM blocks include a first PIM block allocated to at least one first bank and a second PIM block allocated to at least one second bank. The address generating unit of the first PIM block is configured to generate a first internal row address for the at least one first bank, and the address generating unit of the second PIM block is configured to generate a second internal row address for the at least one second bank.