PIM Memory Controller Channel Remapping for Thermal Optimization

The patent merges memory and processor units into an integrated PIM device where processing elements are embedded within the memory structure. This allows data to be processed in-place without external data movement, resolving the contradiction by combining separate components to achieve both integration benefits and maintained complexity manageability through modular design.

The patent introduces a new architectural dimension by embedding processing elements within the memory hierarchy itself, creating a three-dimensional integrated structure. This dimensional transformation enables simultaneous access to storage and processing functions, improving data communication speed while managing system complexity through spatial organization.

The patent segments the computational workload by distributing processing elements across multiple memory banks and channels. Each processing element handles specific neural network operations locally, dividing the exponential computation burden into manageable parallel segments that can be executed simultaneously, thus improving AI performance while controlling power requirements.

The patent enables continuous computation by maintaining data in memory during processing operations rather than requiring repeated data movement. Processing elements continuously operate on data residing in adjacent memory cells, eliminating idle time and ensuring continuous useful action throughout the computational pipeline, which improves efficiency for deep neural networks.

The patent applies local quality by providing processing elements only where needed within specific memory banks, rather than uniformly across the entire device. Each memory bank contains processing elements optimized for its specific data access patterns, creating locally tailored functionality that improves processing speed while managing overall device complexity through selective integration.

The patent implements universal processing elements that can perform multiple operations (read, write, compute, and data movement) within the memory structure. These multi-functional elements reduce the need for separate dedicated circuits for each function, improving data processing speed while controlling device complexity through component versatility.