PIM Memory Device Segmentation for Operation Collision Avoidance
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in processing operations due to the collision of memory operation requests with processing operations, leading to performance deterioration.
Innovation Solution
A memory device with a processor-in-memory (PIM) circuit and control logic that decodes commands/address to perform either memory operations or processing operations based on the decoding result, allowing for independent processing by the PIM circuit without colliding with memory operation requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory operation requests are processed by the memory device, then data storage and retrieval operations are performed, but processing operations collide with memory operations leading to performance deterioration
Solution Approach 1:
The memory device is segmented into distinct functional units: a memory bank for storage operations and a separate PIM circuit for processing operations. This segmentation allows memory operations and processing operations to occur independently in separate units, preventing collisions between the two types of operations and thereby maintaining both high productivity and reliable performance stability.
2Productivity
If processing operations are performed using PIM circuit, then operation processing capability is enhanced, but collisions with memory operation requests occur leading to performance deterioration
Solution Approach 1:
The system divides functionality into separate segments: the memory bank handles storage operations while the PIM circuit handles processing operations. This spatial and functional segmentation ensures that processing operations in the PIM circuit do not interfere with or collide with memory operation requests in the memory bank, enabling enhanced processing capability while maintaining consistent and reliable performance.
3Device complexity
If memory and processing operations share the same device, then integration and compactness are achieved, but operation collisions occur reducing overall efficiency
Solution Approach 1:
The patent merges the memory bank and PIM circuit into a single integrated memory device. The memory bank and PIM circuit are combined in one device package, allowing memory operations and processing operations to coexist in the same physical device without external communication overhead, thereby achieving high integration while preventing operation collisions through internal separation of functions.
Data Source
AI summary
A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.