PIM Memory Controller for Direct Nonvolatile Memory Access
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Solution Overview
Problem
Nonvolatile memory, such as flash memory, has low operation speed and limited use due to latency caused by command protocols and host processor intervention, hindering its integration in high-speed AI processing architectures like Processing-In-Memory (PIM) processors.
Innovation Solution
A memory controller embedded in a PIM processor directly controls nonvolatile memory through serial clock and data signals, incorporating read and write protocol converters and a written sector checker to enable direct access akin to volatile memory, reducing latency by bypassing host processor commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nonvolatile memory is accessed through host processor commands, then data persistence is maintained, but operation speed decreases due to latency
Solution Approach 1:
A memory controller is introduced as an intermediary component between the host processor and nonvolatile memory. The memory controller handles command generation and protocol conversion, allowing the host processor to issue simple read/write requests while the memory controller translates these into the appropriate command sequences for the nonvolatile memory, thereby reducing the latency associated with direct host processor intervention.
Solution Approach 2:
The memory controller pre-generates and buffers command sequences for common operations. When the host processor issues a read or write request, the memory controller can immediately execute pre-prepared commands without waiting for the host processor to generate each command step-by-step, thus reducing operational latency while maintaining data persistence.
2Measurement precision
If host processor intervenes for each command, then command accuracy is ensured, but time overhead increases
Solution Approach 1:
The memory controller is designed to autonomously generate and manage command sequences for nonvolatile memory operations. Instead of requiring the host processor to intervene for each command, the memory controller self-manages the complex protocol requirements, ensuring command accuracy through built-in validation logic while significantly reducing time overhead by eliminating repeated host processor involvement.
3Quantity of substance
If nonvolatile memory is used in PIM processor, then memory capacity is increased, but access efficiency decreases due to protocol complexity
Solution Approach 1:
The memory controller is designed with multi-functional capabilities to handle various nonvolatile memory types and protocols through a unified interface. It can manage different memory organizations, command sets, and data formats, allowing the PIM processor to access diverse nonvolatile memory configurations efficiently without requiring separate control logic for each memory type, thereby improving access efficiency while maintaining high memory capacity.
Data Source
AI summary
Disclosed herein is an apparatus and method for controlling nonvolatile memory. The apparatus may include nonvolatile memory and a memory controller for issuing a serial clock (SCK) to the nonvolatile memory and transferring data corresponding to a requested command to the nonvolatile memory or receiving data corresponding to a requested command from the nonvolatile memory and outputting the data to the outside through a serial-in or a serial-out in response to a read request or a write request.