PIM Memory Management for DRAM Access Optimization
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Solution Overview
Problem
Processing-in-memory (PIM) systems face performance degradation due to high hardware complexity and inefficient memory access times, particularly in open-page mode, which affects the performance of dynamic random access memory (DRAM) within these systems.
Innovation Solution
The proposed memory management method involves altering the processing order of memory addresses in PIM instructions and using a page closing signal to optimize DRAM operations, thereby improving the open page hit rate and reducing performance losses associated with page misses by secondary requesting destination addresses and maintaining previous memory addresses for comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the processing unit supports complex operations to improve PIM functionality, then processing capability is improved, but hardware complexity increases
Solution Approach 1:
A memory management unit (MMU) is introduced as an intermediary component between the processing unit and DRAM. The MMU handles complex memory management tasks including address translation, cache control, and page management, allowing the processing unit to maintain simplicity while achieving enhanced functionality through the MMU's mediation
2Speed
If DRAM is accessed frequently to improve processing speed, then system performance is improved, but memory transaction time increases
Solution Approach 1:
The system performs preliminary actions by pre-loading data into cache memory before it is actually needed by the processing unit. The MMU predicts future memory access patterns and prepares data in advance, reducing the actual transaction time when data is needed and improving overall processing speed without increasing critical path latency
Solution Approach 2:
A hierarchical memory structure is implemented where cache memory is nested within the PIM unit and DRAM is nested outside. This nested architecture allows frequently accessed data to be stored in the faster, smaller cache memory that is physically nested inside the PIM unit, while less frequently accessed data resides in the larger DRAM, optimizing the balance between access speed and storage capacity
3Speed
If open-page mode is used to improve DRAM access efficiency, then memory operation speed is improved, but open page hit rate decreases
Solution Approach 1:
The MMU implements feedback mechanisms that monitor DRAM access patterns and dynamically adjust page management strategies. When page miss rates increase, the system learns from these misses and modifies future page selection and retention decisions, creating a closed-loop control system that continuously optimizes the open page hit rate while maintaining high memory operation speeds
Data Source
AI summary
This application relates to a memory management method for maximizing processing-in-memory (PIM) performance and reducing unnecessary DRAM access time. In one aspect, when processing a PIM instruction packet, an instruction processing unit secondarily processes a request for access to a destination address at which read and write actions of an internal memory are likely to be sequentially performed. By secondarily requesting the destination address, a row address of an open page of the internal memory may match a row address to which a PIM instruction packet processing result is written back. Also, the instruction processing unit inside the PIM maintains memory write and read addresses that have previously requested. The instruction processing unit compares the address of a packet to be processed to the maintained previous memory address and informs a memory controller about the comparison result through a page closing signal.