PIM Memory Bank Dual-Path Operand Selection for Faster MAC
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Solution Overview
Problem
Existing memory devices struggle with inefficient performance in executing multiply and accumulate (MAC) operations for convolutional neural networks due to the need for multiple address accesses and limited parallel processing capabilities, particularly in processing in memory (PIM) operations.
Innovation Solution
The memory device incorporates a memory bank module with a PIM block, utilizing a row buffer and selecting module to transmit first and second data through separate data paths, allowing simultaneous operation of operands within the memory bank, and includes a multiplexer system to manage column group bits for enhanced parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory devices perform MAC operations through multiple operations on memory bank addresses, then computational operations can be completed, but computational acceleration is limited and bandwidth utilization is reduced
Solution Approach 1:
The column address is divided into two sub-column addresses (first sub-column address and second sub-column address), allowing the selecting module to simultaneously select paired operands from the row buffer. This segmentation enables parallel data retrieval and feeds both operands to the PIM block concurrently, achieving computational acceleration without requiring multiple sequential memory bank address operations.
2Productivity
If conventional memory devices use single data path for operand transmission, then device complexity is reduced, but bandwidth utilization is limited
Solution Approach 1:
The patent introduces a second data path in parallel with the first data path, transitioning from a single-dimensional data transmission approach to a two-dimensional parallel transmission structure. The first data path transmits the first operand while the second data path simultaneously transmits the second operand to the PIM block, effectively doubling the bandwidth utilization for MAC operations without significantly increasing overall device complexity.
Data Source
AI summary
A memory device includes: a memory bank module comprising a memory bank; and an operation module comprising a processing in memory (PIM) block, wherein the memory bank comprises: an array of memory cells arranged in a plurality of rows and a plurality of columns; a row buffer configured to store data of a row corresponding to a row address among the plurality of rows; and a selecting module configured to select first data and second data corresponding to a column address from among the data stored in the row buffer, wherein the first data is transmitted to the PIM block through a first data path connected between the selecting module and the PIM block, and the second data is transmitted to the PIM block through a second data path connected between the selecting module and the PIM block.