PIM Memory Error Logging for Rapid Host Reporting
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Solution Overview
Problem
Existing memory devices fail to quickly recognize and report various types of errors during in-memory processing (PIM) operations, leading to potential miscommunication with the central processing unit.
Innovation Solution
The memory device includes a logic circuit that performs PIM command execution, generates error data, and records it in a log register, with the ability to output event data indicating the existence of errors through different channels in response to specific commands and addresses, allowing for rapid error reporting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the error correction code block notifies the central processing unit of an error during PIM operation, then the error is detected, but the central processing unit fails to recognize the error quickly
Solution Approach 1:
The patent segments the error notification function by creating separate dedicated channels (first channels for error data, second channels for event data) independent from the main data processing path. This allows error information to be transmitted separately and immediately to the host without waiting for normal read operations, thus resolving the contradiction between reliable error detection and fast error recognition.
Solution Approach 2:
The patent introduces a log register as an intermediary component that stores error data generated by the logic circuit. This log register acts as a buffer between the error occurrence in the PIM operation and the host system, allowing errors to be captured and then reported through dedicated event data channels, thereby enabling both reliable detection and quick recognition.
2Device complexity
If the memory device outputs error data through the same channel as normal data, then the communication interface is simple, but the host cannot quickly distinguish and respond to errors
Solution Approach 1:
The patent divides the communication interface into multiple segmented channels: first channels for transmitting error data from the logic circuit to the log register, second channels for transmitting event data (error status) to the host, and third channels for transmitting actual error data to the host. This segmentation allows error information to be separated from normal data traffic, enabling the host to quickly identify and respond to errors without sifting through normal data operations.
3Adaptability or versatility
If the logic circuit performs PIM command execution, then in-memory processing capability is enhanced, but error types become more varied and harder to recognize quickly
Solution Approach 1:
The patent implements a universal error handling architecture where the logic circuit handles multiple PIM operations and various error types through a unified error data generation and reporting mechanism. The same first channels, log register, and event data output structure handle all error types regardless of their source or nature, making the system versatile for different PIM operations while maintaining consistent and quick error recognition across all operation types.
Data Source
AI summary
A memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit performing a read operation on data stored in the plurality of memory banks based on a first command and a first address received from a host. When a PIM instruction set is stored before the first command and the first address are received, the logic circuit is configured to perform a PIM command execution operation. When an error associated with the PIM command execution operation occurs, the logic circuit is configured to generate error data and record the error data at the log register through the first channels. The logic circuit is configured to output event data indicating an existence of the error data to the host in a first operation mode. The logic circuit is configured to output the error data to the host in a second operation mode.