PIM Memory NAND Strings Bitwise Multiplication
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Solution Overview
Problem
Memory bandwidth and latency act as performance bottlenecks in processing systems, particularly when multiple accesses are required from stacked memory devices, impacting efficiency and power consumption.
Innovation Solution
A nonvolatile memory device and processing-in-memory (PIM) method that includes a memory cell array with NAND strings connected to bitlines, an input current generator, and an operation cell array with switching transistors for parallel bitwise multiplications and analog additions, reducing data transfer between the memory device and external devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked memory devices are used to increase memory capacity, then memory capacity is improved, but inter-device bandwidth and inter-device latency worsen processing efficiency
Solution Approach 1:
The patent merges memory storage function with data processing function into a single integrated device. The memory device performs bitwise multiplications and analog additions internally using the stored data, eliminating the need to transfer data between separate memory and processing devices, thus resolving the bandwidth and latency bottlenecks while maintaining high memory capacity through stacking.
Solution Approach 2:
The memory device is designed to perform multiple functions: it stores data in its high-capacity stacked structure and simultaneously performs computational operations (bitwise multiplications and analog additions) on the stored data. This multi-functionality allows the device to act as both memory and processor, improving processing efficiency without sacrificing memory capacity.
2Quantity of substance
If multiple accesses are required from stacked memory devices, then memory capacity is improved, but bandwidth and latency penalties worsen
Solution Approach 1:
By combining memory storage and data processing in the same device, the patent eliminates repeated data transfers between memory and processor that consume significant power. The computational operations are performed directly on the stored data within the memory device, reducing bandwidth penalties and power consumption associated with multiple accesses.
3Productivity
If data transfer between memory device and external devices is reduced, then processing efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the processing function into basic computational units (bitwise multiplication units and analog addition units) that can be integrated within the memory device. This segmentation allows the device to perform data-intensive operations internally without requiring complex external processing systems, thus improving processing efficiency while managing device complexity through modular functional units.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces processing time and power consumption by performing data-intensive operations like MLP, RNN, and CNN through parallel bitwise multiplications and analog additions within the memory device, enhancing processing efficiency.
Implementation Method 1
second ends of the plurality of NAND strings output a plurality of multiplication bits corresponding to bitwise multiplication of the multiplicand data stored in the plurality of NAND strings and multiplier data loaded on the plurality of bitlines
Implementation Method 2
the plurality of switching transistors selectively sum the plurality of input currents based on the plurality of multiplication bits to output a plurality of output currents
Implementation Method 3
The analog-to-digital converter converts the plurality of output currents to a plurality of digital values
Data Source
AI summary
A nonvolatile memory device includes a memory cell array, an input current generator, an operation cell array and an analog-to-digital converter. The memory cell array includes NAND strings storing multiplicand data, wherein first ends of the NAND strings are connected to bitlines and second ends of the NAND strings output multiplication bits corresponding to bitwise multiplication of the multiplicand data stored in the NAND strings and multiplier data loaded on the bitlines. The input current generator generates input currents. The operation cell array includes switching transistors. Gate electrodes of the switching transistors are connected to the second ends of the NAND strings. The switching transistors selectively sum the input currents based on the multiplication bits to output the output currents. The analog-to-digital converter converts the output currents to digital values.