PIM Memory MAC Architecture for Space-Efficient Partial Sums
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Solution Overview
Problem
Current semiconductor memory devices face limitations in performing complex operations like multiply-accumulation (MAC) and partial sum operations due to space constraints in the RAM, leading to inefficiencies and bottlenecks in processing.
Innovation Solution
The proposed solution involves a memory device with a Processing in Memory (PIM) unit that includes multiple MAC operators. These operators perform multiply-accumulation operations in a first stage and partial sum operations in a second stage, allowing for efficient processing within the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all necessary operators are included in the RAM to perform operations directly, then processing capability is improved, but space limitation prevents inclusion of all operators
Solution Approach 1:
The processing operations are segmented into two distinct stages: MAC operations performed by MAC operators in the first stage, and partial sum operations performed by adders in the second stage. This segmentation allows the system to perform complex operations while using less space than would be required if all operators were included simultaneously.
Solution Approach 2:
The system dynamically switches between different operational modes using a stage information signal that controls multiplexers. The MAC operators can operate in either MAC mode or partial sum mode depending on the current stage, allowing the same hardware resources to be reused across different operational phases, thereby reducing the total space required.
2Speed
If multiple MAC operators are used to perform MAC operations, then processing speed is improved, but space consumption increases
Solution Approach 1:
The MAC operators are designed to perform multiple functions: they execute MAC operations during the first stage and partial sum operations during the second stage. This multi-functionality allows the system to achieve high processing speed through parallel MAC operations while controlling space consumption by reusing the same operators across different operational phases.
Solution Approach 2:
A stage information signal dynamically controls the operation mode of each MAC operator through multiplexers. During the first stage, the signal configures operators for MAC operations; during the second stage, it reconfigures them for partial sum operations. This dynamic reconfiguration enables high-speed parallel processing without requiring dedicated hardware for each operation type.
3Adaptability or versatility
If adders are added to perform partial sum operations, then operational completeness is improved, but space limitation is exceeded
Solution Approach 1:
The functionality of adders for partial sum operations is merged with the existing MAC operators. The same MAC operators that perform multiplication and accumulation in the first stage are reused to perform partial sum operations in the second stage, controlled by the stage information signal. This merging eliminates the need for separate adder hardware, achieving operational completeness within the existing space constraints.
Solution Approach 2:
The system uses dynamic control through the stage information signal to reconfigure MAC operators for different functions. When the signal indicates the second stage, the multiplexers route inputs to enable partial sum operations using the same operator structure, providing operational versatility without adding permanent dedicated adder circuits that would consume additional space.
Data Source
AI summary
A memory device includes a memory cell array; and a processing in memory (PIM) unit including a plurality of multiplication and accumulation (MAC) operators which is configured to perform multiply-accumulation operations based on data stored in the memory cell array. The plurality of MAC operators performs the multiply-accumulation operations based on the data in a first stage, and to perform partial sum operations based on result values of the multiply-accumulation operations in a second stage.