Processing-In-Memory Circuit Timing Control for Lower Latency and Power
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Solution Overview
Problem
Existing processing-in-memory (PIM) type memory devices face issues with unnecessary operations and penalties of delay time and power consumption due to strict timing parameters and internal signal toggling during interface and memory operations, affecting process efficiency and power consumption in computing systems.
Innovation Solution
A memory device with a PIM circuit and control logic circuit that allows for reduced timing parameters and power consumption by controlling write and read operations in internal processing modes, minimizing signal toggling and optimizing latency through differential mode settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strict timing parameters are enforced for interface and memory operations, then reliability of data transmission is improved, but delay time and power consumption increase
Solution Approach 1:
The patent segments the operation modes into normal mode and internal processing mode, allowing different timing parameter requirements for different operational contexts. In internal processing mode, the memory device can relax timing constraints since data remains within the device, thereby reducing delay time while maintaining data transmission reliability when interface operations are performed.
Solution Approach 2:
The patent dynamically adjusts timing parameters based on the operational mode. The control logic circuit determines whether to enforce strict timing parameters based on whether interface operations are required, allowing the system to adapt timing constraints in real-time rather than maintaining fixed strict parameters across all operations.
2Reliability
If strict timing parameters are enforced for interface and memory operations, then data transmission reliability is improved, but power consumption increases
Solution Approach 1:
The patent divides operations into segments that require interface communication (normal mode) and those that do not (internal processing mode). By segmenting the operational requirements, the system can apply strict timing parameters only when necessary for external data transmission, reducing unnecessary power consumption from signal toggling during internal operations.
Solution Approach 2:
The control logic dynamically adjusts timing parameter enforcement based on operational mode, reducing power consumption by relaxing constraints during internal processing while maintaining reliability during interface operations. This dynamic adaptation prevents unnecessary energy expenditure on maintaining strict timing for operations that do not require external communication.
3Adaptability or versatility
If internal signals toggle during interface operations, then data transmission functionality is maintained, but power consumption increases
Solution Approach 1:
The patent segments signal toggling behavior based on operational mode. During internal processing mode, the control logic prevents unnecessary internal signal toggling that would occur in normal interface operations, thereby reducing power consumption while maintaining the ability to perform data transmission when needed in normal mode.
Data Source
AI summary
A memory device for reducing timing parameters and power consumption for an internal processing operation and a method of implementing the same are provided. The memory device includes a memory cell array, a processing-in-memory (PIM) circuit configured to perform a processing operation and a control logic circuit configured to control a normal mode and an internal processing mode. The control logic circuit writes an operation result obtained by the processing operation of the PIM circuit in the internal processing mode in the memory cell array and provides read data read from the memory cell array to the PIM circuit.