Memory Controller PIM Mode Switching

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Solution Overview

Problem

Existing mode switching techniques for processing-in-memory (PIM) memory devices require software modifications and additional operating system support, making them technically and economically infeasible to implement solely through software.

Innovation Solution

A memory controller with a bank group scheduler, arbiter, and PIM management circuit that generates and manages commands for switching between normal and PIM modes, allowing for mode switching without special intervention from the operating system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If mode switching is implemented using only software, then implementation simplicity is improved, but system complexity and OS dependency increase making it infeasible

Engineering Contradiction:

Improveimplementation simplicityVSAvoidsoftware complexity and OS dependency

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent introduces a PIM management circuit as an intermediary component between the host and memory device. This dedicated hardware circuit handles mode switching logic, eliminating the need for complex software implementations and OS modifications while maintaining implementation simplicity

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the software-based mode switching mechanism with a hardware-based PIM management circuit. This substitution eliminates dependency on operating system support and complex software codes, achieving feasible implementation through dedicated hardware logic

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If mode switching is implemented with hardware support, then feasibility is improved, but device complexity increases

Engineering Contradiction:

Improveimplementation feasibilityVSAvoidcontroller structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The PIM management circuit is designed to perform multiple functions: generating PIM commands, managing mode switching between normal and PIM modes, and coordinating with the bank group scheduler. This multi-functionality consolidates complexity into a single dedicated circuit rather than distributing it across multiple components

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The PIM management circuit autonomously handles mode switching based on the number of PIM commands without requiring external software intervention or OS support. The circuit self-regulates the switching between normal and PIM modes, reducing overall system complexity despite adding dedicated hardware

Inventive Principle:

Principle #25Self-service

3Productivity

If mode switching is controlled by number of PIM commands, then scheduling efficiency is improved, but control complexity increases

Engineering Contradiction:

Improvescheduling efficiencyVSAvoidcontrol logic complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent uses the parameter 'number of PIM commands' as a trigger for mode switching control. The PIM management circuit monitors this parameter and automatically switches modes based on threshold conditions, achieving efficient scheduling through simple parameter-based logic rather than complex control algorithms

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20240220127A1Memory controller for supporting processing-in-memory

Publication Date: 2024.07.04 SK HYNIX INC

AI summary

A memory controller controls modes for processing requests for a memory device. The modes include a normal mode for processing a memory request and a processing-in-memory (PIM) mode for processing a PIM request. The memory controller includes a bank group scheduler configured to generate a memory command corresponding to a memory request; an arbiter configured to select and output the memory command; and a PIM management circuit configured to generate a PIM command corresponding to a PIM request. The PIM management circuit controls switching between the normal mode and the PIM mode according to, among other criteria, a number of PIM commands.