Processing-in-Memory Architecture for Neural Network Data Access
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Solution Overview
Problem
Current computer apparatuses are unable to meet the fast and effective operating performance requirements of complex neural network operations due to limited processing speed, which is hindered by shared bus occupancy, preventing real-time data access for AI operations.
Innovation Solution
A memory with a processing-in-memory (PIM) architecture that includes a memory array, mode register, and AI core, allowing for direct data access by an AI core integrated into the memory, with dedicated memory buses for AI and special function processing cores to access different memory regions independently, enhancing data access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a shared bus is used for data access between processing cores and memory, then device complexity is reduced, but data access speed deteriorates due to bus occupancy by other cores
Solution Approach 1:
The memory array is divided into multiple memory regions, with each region dedicated to specific processing cores. The memory array is segmented into first memory regions for AI cores and second memory regions for other processing cores, allowing simultaneous independent access without bus conflicts.
Solution Approach 2:
A memory management unit acts as an intermediary between processing cores and memory regions. The MMU receives memory access requests, determines the corresponding memory region based on core type and request parameters, and routes access appropriately, enabling complex memory management without requiring complex bus arbitration.
2Productivity
If a dedicated processing core is designed for neural network operations, then processing capability is improved, but data access speed deteriorates due to shared bus limitations
Solution Approach 1:
The AI core is integrated directly with the memory system, forming a unified processing-memory architecture. The AI core can directly access first memory regions without going through external buses, combining processing and memory functions to eliminate bus bottlenecks while maintaining dedicated neural network processing capability.
3Productivity
If multiple processing cores access memory simultaneously via shared bus, then processing parallelism is improved, but data access speed deteriorates due to bus occupancy
Solution Approach 1:
The memory array is segmented into multiple independently accessible regions that can be simultaneously accessed by different processing cores. First memory regions are accessible by AI cores while second memory regions are accessible by other processing cores, enabling true parallel access without bus contention.
Data Source
AI summary
A memory with a processing in memory architecture and an operating method thereof are provided. The memory includes a memory array, a mode register, an artificial intelligence core, and a memory interface. The memory array includes a plurality of memory regions. The mode register stores a plurality of memory mode settings. The memory interface is coupled to the memory array and the mode register, and is externally coupled to a special function processing core. The artificial intelligence core is coupled to the memory array and the mode register. The plurality of memory regions are respectively selectively assigned to the special function processing core or the artificial intelligence core according to the plurality of memory mode settings of the mode register, so that the special function processing core and the artificial intelligence core respectively access different memory regions in the memory array according to the plurality of memory mode settings.