Processor-in-Memory Parallel Search for Low-Power Data Matching

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Solution Overview

Problem

Current memory devices face inefficiencies in processing and power consumption when performing text searches or data inquiries, particularly when handling multiple documents or data streams simultaneously, due to the separation of processing resources from memory devices leading to longer delays and increased power usage.

Innovation Solution

The implementation of a processor-in-memory (PIM) device with a two-dimensional array of memory cells that executes arithmetic and Boolean logical operations in parallel across columns, allowing for concurrent comparison of data patterns within data streams stored in the memory array, thereby reducing the need for external processing and minimizing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If processing resources are external to memory devices, then device complexity is reduced and ease of manufacture is improved, but processing delays increase and power consumption increases

Engineering Contradiction:
Improveease of manufactureVSAvoidprocessing delays
Core Design Contradiction:
Ease of manufactureVSLoss of time

Solution Approach 1:

The patent combines processing resources with memory devices by integrating processor circuits directly into the memory device structure. This merging eliminates the need for external processing units and data buses, allowing data to be processed in-place within the memory array, thereby reducing processing delays while maintaining ease of manufacture through standardized integrated circuit fabrication processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent utilizes the two-dimensional array structure of memory cells to enable parallel processing across multiple dimensions. By organizing processing elements to operate simultaneously on multiple data elements stored in the memory array, the system achieves high-speed parallel processing without requiring external processing resources, thus reducing processing delays while maintaining manufacturing simplicity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If processing resources are external to memory devices, then device complexity is reduced and ease of manufacture is improved, but power consumption increases

Engineering Contradiction:
Improveease of manufactureVSAvoidpower consumption
Core Design Contradiction:
Ease of manufactureVSUse of energy by moving object

Solution Approach 1:

The patent combines processing resources with memory devices by integrating processor circuits directly into the memory device structure. This merging eliminates the need for external processing units and data buses, allowing data to be processed in-place within the memory array, thereby reducing processing delays while maintaining ease of manufacture through standardized integrated circuit fabrication processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory device performs processing operations independently using integrated processor circuits, eliminating the need to transfer data externally for processing. This self-service capability reduces power consumption by avoiding repeated data transfers over power-consuming buses and enables the memory device to autonomously execute search and processing operations on stored data.

Inventive Principle:
Principle #25Self-service

3Device complexity

If data is transferred via bus between processing resources and memory devices, then device complexity is reduced, but processing speed decreases and power consumption increases

Engineering Contradiction:
Improvedevice complexityVSAvoidprocessing speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent combines processing resources with memory devices by integrating processor circuits directly into the memory device structure. This merging eliminates the need for external processing units and data buses, allowing data to be processed in-place within the memory array, thereby reducing processing delays while maintaining ease of manufacture through standardized integrated circuit fabrication processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent utilizes the two-dimensional array structure of memory cells to enable parallel processing across multiple dimensions. By organizing processing elements to operate simultaneously on multiple data elements stored in the memory array, the system achieves high-speed parallel processing without requiring external processing resources, thus reducing processing delays while maintaining manufacturing simplicity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Device complexity

If data is transferred via bus between processing resources and memory devices, then device complexity is reduced, but power consumption increases

Engineering Contradiction:
Improvedevice complexityVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent combines processing resources with memory devices by integrating processor circuits directly into the memory device structure. This merging eliminates the need for external processing units and data buses, allowing data to be processed in-place within the memory array, thereby reducing processing delays while maintaining ease of manufacture through standardized integrated circuit fabrication processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory device performs processing operations independently using integrated processor circuits, eliminating the need to transfer data externally for processing. This self-service capability reduces power consumption by avoiding repeated data transfers over power-consuming buses and enables the memory device to autonomously execute search and processing operations on stored data.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10489060B2Searching data in parallel using processor-in-memory devices
Publication Date: 2019.11.26 MICRON TECHNOLOGY INC
  • US10489060B2 patent drawing
  • US10489060B2 patent drawing
  • US10489060B2 patent drawing

AI summary

A method includes comparing, in parallel, a data pattern with data stored into a plurality of columns of memory cells, and in response to detecting the data pattern in the data stored into a particular column of memory cells of the plurality of columns of memory cells, storing in a memory cell of the particular column a value indicative of at least one of an occurrence of the data pattern or a position of the data pattern in the data stored into the particular column.