Processing-in-Memory for Spiking Neural Network Spike Filtering
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Solution Overview
Problem
Conventional computing systems face challenges in processing spiking events in spiking neural networks (SNNs) due to high bandwidth requirements and inefficient data transmission, leading to processor- and memory-intensive operations that consume significant power and time.
Innovation Solution
Implementing processing-in-memory (PIM) operations within a PIM-capable memory device, which includes a memory array coupled to sensing circuitry, allowing for bit vector operations and filtering of spiking events directly within the memory, reducing the need for external data transfer and enhancing processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is accessed via a bus between external processing resources and memory array, then processing operations can be performed, but processing performance is limited and power consumption increases due to external communications
Solution Approach 1:
The patent combines processing resources and memory array into a single integrated device, eliminating the need for external data transmission via bus. The processing resources are positioned within or near the memory array, allowing data to be processed in-place without being moved to external processors, thereby improving processing performance while reducing power consumption associated with external communications
Solution Approach 2:
The patent introduces local processing circuitry as an intermediary between the memory array and external processors. This intermediary enables data to be processed within the memory device itself, reducing the need for frequent data transfers over the bus and thereby lowering power consumption while maintaining or improving processing performance
2Device complexity
If processing resources are implemented externally to memory array, then device complexity is reduced, but data transmission bandwidth requirements increase and latency increases
Solution Approach 1:
The patent merges processing resources with the memory array into an integrated processing-in-memory device. This combination eliminates the need for data to be transferred between external processors and memory, significantly reducing latency. While the device complexity increases due to integration, the performance benefits in terms of reduced latency and improved bandwidth efficiency justify the added complexity
3Ease of manufacture
If processing resources are implemented externally to memory array, then ease of manufacture is improved, but data transmission bandwidth requirements increase
Solution Approach 1:
The patent integrates processing resources directly with the memory array, enabling data to be processed in-place without requiring high-bandwidth external data transmission paths. This reduces the bandwidth requirements for data transmission between memory and processor, as data remains localized within the integrated device throughout the processing operation
Data Source
AI summary
Methods, apparatuses, and systems for in- or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store a group of destination neurons, and at each time interval in a series of time intervals of a spiking neural network (SNN), pass through a group of pre-synaptic spike events from respective source neurons, wherein the group of pre-synaptic spike events are subsequently stored in memory.