PIM Memory Sub-Channel Partitioning for Concurrent Access
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Solution Overview
Problem
As the amount of instructions and data stored in memory systems increases, performance decreases due to increased latency and power consumption in transferring, storing, and retrieving information, particularly in battery-operated devices with high memory usage and quality of service requirements.
Innovation Solution
A memory system with a first and second sub-channel interface, where the second sub-channel interface is deactivated during a particular mode of operation to perform PIM operations concurrently with memory access commands through the first sub-channel interface, allowing for concurrent PIM operations and memory access operations without interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the amount of instructions and data stored in memory systems increases, then the memory capacity increases, but the performance decreases due to increased latency and power consumption
Solution Approach 1:
The memory system is divided into multiple memory banks (first plurality and second plurality) with associated PIM blocks, allowing parallel processing operations across different segments to improve throughput while maintaining high capacity
Solution Approach 2:
Processing capabilities are integrated directly into the memory structure through PIM blocks associated with each memory bank, adding a computational dimension to the traditional storage hierarchy and enabling data processing at the memory location
2Speed
If data is transferred, stored, and retrieved between host and memory system, then the data access capability increases, but the power consumption increases
Solution Approach 1:
PIM blocks perform processing operations autonomously on data within memory banks without requiring constant host intervention, enabling the memory system to service itself and reduce power-consuming data transfers between host and memory
3Productivity
If PIM operations are performed concurrently with memory access commands, then the processing throughput increases, but the interface complexity increases
Solution Approach 1:
The memory interface is segmented into multiple independent sub-channels, each capable of handling memory access commands and PIM operations separately, allowing concurrent operations without requiring a single complex unified interface
Data Source
AI summary
A memory system includes a memory interface including a first sub-channel interface associated with a first plurality of memory banks and a first plurality of processor in memory (PIM) blocks and further including a second sub-channel interface associated with a second plurality of memory banks and a second plurality of PIM blocks. During a particular mode of operation associated with the memory system, the first sub-channel interface is configured to communicate, with a host device, one or more memory access commands associated with the first plurality of memory banks. During the particular mode of operation, the second plurality of PIM blocks are configured to perform, concurrently with communication of the one or more memory access commands, one or more PIM operations associated with the second plurality of memory banks. The second sub-channel interface is configured to be disabled during the particular mode of operation.