PIM and Non-PIM Thread Scheduling with Dynamic Mode Switching
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Solution Overview
Problem
Conventional computer architectures with processing-in-memory (PIM) components face challenges in scheduling PIM and non-PIM requests due to irregular arrival intervals and static threshold-based mode switching, leading to inefficient resource consumption, latency, and degraded performance.
Innovation Solution
A memory controller employs a three-stage arbitration system to dynamically schedule PIM and non-PIM requests based on priority and current operating mode, using separate queues and adaptive priority assignment to optimize system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If static threshold-based mode switching is used to schedule PIM and non-PIM requests, then the scheduling mechanism is simple to implement, but system performance is degraded due to irregular arrival intervals and inefficient resource consumption
Solution Approach 1:
The patent implements dynamic mode switching between PIM and non-PIM operations based on real-time system state and request characteristics. The memory controller continuously monitors request patterns and adjusts scheduling modes adaptively, transitioning from static threshold-based scheduling to dynamic policy-based scheduling that responds to actual workload conditions, thereby improving system performance while maintaining manageable complexity
Solution Approach 2:
The patent changes scheduling parameters dynamically based on request types and system state. Different scheduling policies are applied for PIM versus non-PIM requests, and the system adjusts timing parameters, priority levels, and mode switching thresholds based on observed workload patterns, enabling optimized performance without requiring complete redesign of the scheduling mechanism
2Adaptability or versatility
If conventional scheduling techniques are extended to handle both PIM and non-PIM requests, then the scheduling coverage is increased, but resource consumption efficiency decreases
Solution Approach 1:
The patent segments the scheduling mechanism into separate handling paths for PIM and non-PIM requests. The memory controller identifies request types and applies specialized scheduling policies for each category, allowing optimized resource allocation for PIM operations (which benefit from proximity to memory) while maintaining efficient scheduling for traditional non-PIM requests, thereby improving overall resource consumption efficiency while maintaining broad scheduling coverage
Solution Approach 2:
The memory controller is designed with multi-functional scheduling capabilities that can handle both PIM and non-PIM requests through a unified control structure. The same memory controller hardware performs both types of scheduling operations, but with differentiated policies that optimize for each request type's specific characteristics, achieving versatility without proportionally increasing resource consumption
3Speed
If PIM requests are prioritized to reduce data transfer latency, then memory access speed is improved, but non-PIM request handling may be delayed
Solution Approach 1:
The patent implements periodic mode switching between PIM-optimized and non-PIM-optimized scheduling. Rather than continuously prioritizing PIM requests, the system alternates between modes that favor PIM operations and modes that favor non-PIM operations, based on request arrival patterns and system state. This periodic alternation ensures that PIM requests receive timely handling when present, while non-PIM requests are serviced during their designated periods, balancing memory access speed improvement with fair non-PIM request latency
Solution Approach 2:
The system dynamically changes scheduling parameters such as priority levels, queue depths, and mode switching thresholds based on the mix of PIM and non-PIM requests. When PIM requests are prevalent, parameters are adjusted to optimize memory access speed; when non-PIM requests dominate, parameters shift to reduce their latency. This adaptive parameter adjustment balances the competing speed and latency requirements
Data Source
AI summary
Scheduling requests of multiple processing-in-memory threads and requests of multiple non-processing-in-memory threads is described. In accordance with the described techniques, a memory controller receives a plurality of processing-in-memory threads and a plurality of non-processing-in-memory threads from a host. The memory controller schedules an order of execution for requests of the plurality of processing-in-memory threads and requests of the plurality of non-processing-in-memory threads based on a priority associated with each of the requests and a current operating mode of the system. Requests are maintained in queues at the memory controller and are individually assigned a priority level based on time enqueued at the memory controller. Requests of a different mode than a current operating mode of the system are delayed for scheduling until at least one different mode request is escalated to a maximum priority value, at which point the memory controller initiates a system mode switch.