Processor-in-Memory Tile-Based Graphics Rendering
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Solution Overview
Problem
Computing systems face limitations in processing performance due to limited resources, particularly in image and video processing, where communication bandwidth between processors and memory is restricted, leading to increased energy consumption and reduced efficiency.
Innovation Solution
A computing system is designed with a memory device containing a processor-in-memory (PIM) that offloads specific stages of the graphics pipeline for tile-based rendering from the host processor, optimizing memory bandwidth and reducing power consumption by integrating processing functions within the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the host processor performs the entire graphics pipeline, then processing control is centralized, but processing performance is limited due to resource constraints and bandwidth bottlenecks
Solution Approach 1:
The graphics pipeline is divided into two independent sub-pipelines: a first sub-pipeline executed by the internal processor in the memory device and a second sub-pipeline executed by the host processor. This segmentation allows each processor to handle specific tasks, improving overall processing performance while distributing computational burden and reducing bandwidth requirements for data transfer between processors and memory.
2Use of energy by stationary object
If processing functions are integrated within the memory device, then memory bandwidth is optimized and power consumption is reduced, but the memory device must support additional processing capabilities
Solution Approach 1:
The patent merges processing functionality with the memory device by incorporating an internal processor that can execute the first sub-pipeline of the graphics pipeline. This integration allows data processing to occur closer to where data is stored, reducing the need for data to be transported over the memory bandwidth interface and thereby lowering power consumption while enabling the memory device to perform both storage and computation functions.
3Productivity
If the internal processor in memory device performs offload processing, then memory access and bandwidth usage are minimized, but coordination complexity between processors increases
Solution Approach 1:
The patent introduces a controller as an intermediary component that manages coordination between the host processor and the internal processor in the memory device. The controller receives control signals from the host processor, determines which sub-pipeline stages should be executed by the internal processor, and coordinates the execution of both sub-pipelines. This intermediary simplifies the coordination complexity by centralizing the decision-making logic for task distribution.
Data Source
AI summary
A computing system includes a memory device comprising a memory array and an internal processor configured to perform a first sub pipeline of a graphics pipeline for tile-based rendering by using graphics data stored in the memory array, for offload processing of the first sub pipeline from a host processor; and the host processor configured to perform a second sub pipeline of the graphics pipeline by using a result of the first sub pipeline stored in the memory array.