Patterned Insulation Metal Substrate for Power Module Heat Dissipation
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Solution Overview
Problem
Traditional power module packages have a poor ability to dissipate heat due to their structural design, which adversely affects their reliability.
Innovation Solution
A patterned insulation metal substrate (PIMS) is introduced, featuring a metal carrier with a patterned insulation layer partially covering it and a patterned conductive layer on top, allowing for improved heat dissipation by exposing parts of the carrier to the environment, and incorporating semiconductor chips and passive components connected via conductive units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full-faced insulation layer is used on the metal carrier, then electrical insulation is improved, but heat dissipation ability deteriorates
Solution Approach 1:
The insulation layer is segmented into patterned regions rather than being continuous. The patterned insulation layer includes insulated regions over conductive traces and exposed regions where the metal carrier is directly accessible, allowing heat to dissipate through direct contact with the carrier while maintaining electrical insulation where needed.
Solution Approach 2:
Different regions of the substrate have different insulation properties. Areas requiring electrical insulation have the insulation layer, while areas requiring heat dissipation have the metal carrier exposed. This local differentiation allows simultaneous optimization of both electrical insulation and thermal management in different locations.
2Reliability
If the metal carrier is fully covered by insulation layer, then electrical insulation is improved, but thermal conductivity deteriorates
Solution Approach 1:
The insulation layer is divided into patterned regions rather than being continuous. Exposed regions of the metal carrier allow thermal energy to escape efficiently, while insulated regions maintain electrical isolation. This segmentation enables simultaneous optimization of thermal energy loss and electrical insulation.
3Ease of manufacture
If traditional stacked substrate structure is used, then manufacturing simplicity is maintained, but heat dissipation performance deteriorates
Solution Approach 1:
The insulation layer is selectively removed or not applied in certain regions to expose the metal carrier. This extraction of the insulation material in specific areas creates direct thermal pathways from power chips to the carrier while maintaining the overall simplicity of the stacked substrate structure.
Solution Approach 2:
The substrate structure transitions from uniform to non-uniform, with different regions having different compositions. Areas with power chips have exposed metal carrier for heat dissipation, while other areas maintain the full insulation layer for electrical isolation, achieving local optimization without complex overall structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The PIMS design enhances heat dissipation and reliability of power module packages by allowing direct heat transfer from chips to the metal carrier, improving the overall performance and longevity of the modules.
Implementation Method 1
The PIMS design enhances heat dissipation and reliability of power module packages by allowing direct heat transfer from chips to the metal carrier
Implementation Method 2
a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier
Data Source
AI summary
A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.