Pin Accessibility Prediction Engine for Advanced Node DRV Reduction
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Solution Overview
Problem
Existing electronic design automation tools face challenges in predicting pin accessibility in advanced process nodes, as deterministic approaches are ineffective due to complexity, and machine learning methods relying on global routing congestion and pin density are not strongly correlated with design rule violations.
Innovation Solution
A Pin Accessibility Prediction Engine (PAPE) using a design-level CNN-based architecture and active learning-based cell library-level approach to identify pin patterns likely to result in design rule violations by training on quantified pixelated pin patterns and iteratively refining the model with critical pin patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deterministic approaches based on human knowledge are used to solve pin accessibility problems, then the approach is simple and interpretable, but the effectiveness is limited due to extreme complexity in advanced nodes
Solution Approach 1:
The patent replaces deterministic mechanical/rules-based approaches with a machine learning model (CNN-based predictor) that automatically learns patterns from training data. This substitution enables the system to handle the extreme complexity of advanced node designs by leveraging data-driven insights rather than human-defined rules, directly improving prediction effectiveness while managing complexity through automation.
Solution Approach 2:
The patent changes the approach from using fixed human knowledge parameters to dynamically learned parameters from training data. The CNN model learns optimal feature representations and decision boundaries from labeled training examples, allowing the system to adapt to varying complexities across different design nodes and scenarios, thereby improving reliability without being constrained by static deterministic rules.
2Extent of automation
If machine learning methods using global routing congestion and pin density are used, then automation is improved, but prediction accuracy is reduced because DRV occurrence is not strongly correlated with these features
Solution Approach 1:
The patent extracts and removes the ineffective features (global routing congestion and pin density) from the prediction model and replaces them with pin pattern-based features. By taking out the correlated-but-ineffective features and focusing on the actual critical features (pin patterns), the model achieves both automation and improved accuracy in predicting DRV occurrences.
Solution Approach 2:
The patent shifts from global-level features (overall routing congestion) to local-level features (specific pin patterns). The CNN model analyzes local pin arrangement configurations rather than global metrics, enabling more precise prediction of DRV occurrences by focusing on the actual local conditions that cause accessibility problems.
3Ease of operation
If cell libraries are considerably redesigned to enhance pin accessibility, then pin accessibility improves, but the optimized performance and manufacturability are compromised due to sensitivity to cell layouts
Solution Approach 1:
The patent applies preliminary action by predicting pin accessibility issues before the routing stage using the trained CNN model. By identifying problematic pin patterns in advance during placement or design rule checking, the system allows designers to address accessibility issues early without redesigning entire cell libraries, thus maintaining the optimized performance and manufacturability of foundry-provided libraries while still improving pin accessibility where needed.
Solution Approach 2:
The patent introduces an intermediary prediction system that acts as a mediator between the fixed cell library designs and the routing process. The CNN-based predictor serves as an intermediary tool that identifies accessibility issues without requiring changes to the underlying cell library structures, thereby preserving the libraries' optimized performance while enabling targeted improvements in specific pin accessibility cases.
Data Source
AI summary
An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).