Display Panel Pin Connector Layout for Voltage Isolation
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Solution Overview
Problem
The increasing number of pins in electronic devices leads to issues during plugging, as the fixed size of pin connectors cannot accommodate additional virtual pins to isolate low-voltage and high-voltage pins, resulting in devices inside the display panel being damaged by overloaded voltage signals.
Innovation Solution
A pin connector design with pins arranged along a direction, where a space between pins transmitting different voltages is defined to be at least the size of three pins, incorporating buffer areas to prevent damage from voltage differences during the plugging process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of pins is increased to accommodate more functions, then the functionality of electronic devices is improved, but the risk of pin shifting during plugging increases, causing voltage overload damage
Solution Approach 1:
The patent introduces a buffer area as an intermediary zone between adjacent pins transmitting different voltages. This buffer area acts as a mediator that prevents direct interaction between pins with different voltage levels, thereby eliminating the harmful effect of voltage overload while preserving the increased pin count for enhanced functionality.
2Ease of manufacture
If the size of pin connector is fixed, then the manufacturing cost is reduced, but additional virtual pins cannot be added to isolate low-voltage pins from high-voltage pins
Solution Approach 1:
The patent applies local quality by creating buffer areas specifically at locations where pins with different voltage levels are adjacent to each other. Instead of uniformly increasing the connector size, the buffer areas are locally inserted only where voltage isolation is needed, maintaining cost-effectiveness while providing targeted pin isolation capability.
3Reliability
If buffer areas are added between pins with voltage differences, then the protection against voltage overload is improved, but the space between pins is increased
Solution Approach 1:
The patent implements partial action by inserting buffer areas only between adjacent pins that transmit different voltages, rather than uniformly increasing spacing between all pins. This selective approach provides necessary voltage overload protection while minimizing the overall space occupation, achieving an optimal balance between protection and compactness.
Data Source
AI summary
A pin connector and a display panel are provided in the present application. The pin connector includes a plurality of pins arranged along a first direction, wherein the pins include a first pin for transmitting a first voltage, a second pin for transmitting a second voltage, and the first voltage is lower than the second voltage, wherein in the first direction, a space between the first pin and the second pin is not smaller than a size of three of the pins.