Pin-Control Circuit for Low-Latency I/O Access
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Solution Overview
Problem
In multi-core integrated circuits, existing methods face challenges in providing low-latency and error-free write access to GPIO pins due to software-implemented control logic, which leads to software latency and data corruption issues, especially when multiple cores access shared I/O banks and external devices.
Innovation Solution
A pin-control circuit that uses source identification and pin-control values to determine and manage access to I/O pins independently, preventing unauthorized access and ensuring accurate data updates without software latency, by integrating a pin-control register and control logic circuits to manage access based on core types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-implemented control logic is used to manage I/O pin access, then multiple cores can share I/O banks, but software latency is introduced and system performance is impacted
Solution Approach 1:
The patent replaces software-implemented control logic with hardware-based control logic circuits. The control logic is implemented as dedicated hardware circuits that directly manage I/O pin access, eliminating the software processing steps that cause latency. Each I/O bank has its own control logic circuit that operates independently in hardware, providing immediate response to access requests without software intervention.
Solution Approach 2:
The patent introduces control logic circuits as intermediary hardware components between cores and I/O banks. These control logic circuits act as mediators that manage access requests from multiple cores to I/O pins, using hardware-based arbitration mechanisms to grant access rights without software intervention, thus reducing latency while maintaining coordinated access.
2Loss of time
If dedicated I/O banks are allocated to each core, then access latency is reduced, but I/O pin utilization efficiency decreases and pins remain unused
Solution Approach 1:
The patent implements I/O banks that can serve multiple core types through hardware control logic. The control logic circuits detect the type of core making an access request and dynamically configure the I/O bank to accept requests from different core types. This allows a single I/O bank to function for multiple purposes and serve multiple cores, improving utilization while maintaining low latency through hardware-based access control.
Solution Approach 2:
The patent introduces dynamic configuration capability in the control logic circuits, which can adaptively change the behavior and access permissions of I/O banks based on the type of core requesting access. The control logic dynamically adjusts pin assignment and access rights in hardware, allowing the system to optimize both latency and utilization based on real-time core type identification.
3Productivity
If I/O pins are shared between cores of different types, then pin utilization improves, but data corruption occurs when one core updates pin data intended for another core
Solution Approach 1:
The patent introduces control logic circuits as intermediary hardware components that stand between multiple cores and shared I/O pins. These control logic circuits receive access requests from different core types, verify the requesting core's authorization based on core type matching, and manage the pin data updates. This intermediary hardware layer prevents unauthorized cores from corrupting pin data while allowing authorized sharing, thus maintaining both utilization and data integrity.
Solution Approach 2:
The patent implements feedback mechanisms in the control logic circuits that monitor access requests and verify core type compatibility before allowing I/O pin access. The control logic provides feedback to prevent unauthorized access attempts and ensures that only compatible core types can access specific I/O pins, preventing data corruption while maintaining efficient pin utilization through controlled sharing.
Data Source
AI summary
An integrated circuit (IC) having multiple cores controls write access to its input/output (I/O) pins. The IC includes a pin-control circuit, a memory, and a set of I/O pins. The pin-control circuit allows a core to independently control individual ones of the I/O pins. A set of pin-control values are defined that correspond to the set of I/O pins to indicate a type of core that can access an I/O pin. The pin-control circuit receives the pin-control values, a source ID, and write data generated by a core, and updates a pin data bit stored in the memory with a corresponding bit of the write data when the core is allowed to access the I/O pin. The pin-control circuit does not change the pin data bit when the core is denied write access to the I/O pin.