Pin-Correcting ECC Layout for Multi-Bit Memory Transmission Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing error correction mechanisms in computer systems, particularly those using Galois fields, are not robust enough to handle errors spanning multiple devices and require additional check bits for pin correction during data transmission, which can lead to reduced efficiency and effectiveness in error detection and correction.
Innovation Solution
A memory system employing a pin-correcting ECC scheme with an array of bits organized into rows and columns, including data-bit columns, row check bit columns, and inner check bit columns, using check vectors and polynomials with GF(2) coefficients to facilitate error detection and correction across multiple devices and pins, ensuring robustness against multi-bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing Galois field-based error correction schemes are used for pin correction during data transmission, then error detection capability is provided, but the number of check bits increases reducing efficiency
Solution Approach 1:
The patent segments the error correction functionality by separating row check bits from inner check bits. Row check bits handle row-level errors while inner check bits handle column-level errors. This segmentation allows the system to use only the necessary check bits for pin correction during transmission, rather than applying a full Galois field-based ECC scheme that would require more check bits, thus maintaining error detection capability while improving transmission efficiency.
2Reliability
If additional check bits are added for pin correction, then robustness against multi-bit errors improves, but the complexity of the error correction code increases
Solution Approach 1:
The patent applies local quality by making different parts of the code serve different functions. Row check bits provide local protection against row errors, while inner check bits provide local protection against column errors. This localized approach allows the system to achieve robustness against multi-bit errors without implementing a complex global Galois field-based ECC scheme, thereby reducing overall code complexity while maintaining reliability.
3Productivity
If a simple CRC code is used for soft errors, then transmission efficiency is maintained, but the code cannot correct errors caused by bad pins
Solution Approach 1:
The patent merges CRC error detection with an enhanced error correction mechanism. The row check bits and inner check bits work together to provide both detection and correction capabilities. This merging allows the system to maintain the efficiency of simple codes like CRC while adding the ability to correct errors caused by bad pins, thus resolving the contradiction between transmission efficiency and error correction capability.
Data Source
AI summary
The disclosed embodiments provide a memory system that provides error detection and correction. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including C−M−1 data-bit columns containing data bits, a row check bit column including row-parity bits for each of the R rows in the block, and M inner check bit columns that collectively include MR inner check bits. These inner check bits are defined to cover bits in the array in accordance with a set of check vectors, wherein each check vector is associated with a different bit in the array and is an element of Res(P), a residue system comprising a set of polynomials with GF(2) coefficients modulo a polynomial P with GF(2) coefficients, wherein each column is associated with a different pin in a memory module interface, and wherein the check bits are generated from the data bits to facilitate block-level detection and correction for errors that arise during the transmission. During operation, the system transmits a block of data from the memory. Next, the system uses an error-detection circuit to examine the block of data, and determine whether an error has occurred during the transmission based on the examination.