Pin Driver Calibration via Bypass Circuitry
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Solution Overview
Problem
Existing automated test systems face challenges in providing a compact, low-power, high-fidelity solution for testing electronic devices with minimal loading effects on the device under test, while accommodating diverse test requirements and allowing for user calibration across multiple channels.
Innovation Solution
A partitioned force-sense system utilizing integrated switches and dual-purpose signal paths across different semiconductor substrates and manufacturing processes, enabling selective auxiliary control and calibration, with a per-pin parametric measurement unit (PMU) and driver/comparator circuits optimized for high precision and high bandwidth operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional automated test systems are used, then comprehensive test functionality is provided, but system size and power consumption increase
Solution Approach 1:
The test system is divided into separate functional modules: a parametric measurement unit (PMU) for precision measurements and a driver/comparator circuit for signal generation and detection. These modules can be independently configured and powered, allowing the system to consume power only when specific test functions are active, thereby reducing overall power consumption while maintaining comprehensive test capability.
Solution Approach 2:
The driver circuit is designed to perform multiple functions: it acts as a voltage source for stimulating the DUT, a current source for biasing, and a termination resistor for signal integrity. The comparator circuit similarly serves both as a measurement instrument and as a stimulus generator. This multi-functionality reduces the number of separate components needed, thereby reducing power consumption while maintaining versatile test functionality.
2Area of stationary object
If integrated device structures are used, then die area is minimized, but loading effects at DUT interface increase
Solution Approach 1:
The patent introduces an external resistor connected to the DUT interface that serves as an intermediary element. This external resistor works in conjunction with the integrated device structures to provide the necessary termination and biasing functions without requiring large on-chip resistors, thereby minimizing die area while controlling loading effects through the external component.
Solution Approach 2:
The system allows dynamic adjustment of test parameters including voltage levels, current levels, and termination resistance values. By changing these parameters adaptively based on the specific test requirements and DUT characteristics, the system can minimize loading effects for different test scenarios while maintaining compact integrated structures.
3Adaptability or versatility
If multiple driver circuits with different amplitude and timing characteristics are provided, then diverse test requirements are met, but device complexity increases
Solution Approach 1:
The driver circuit incorporates dynamically controllable parameters including adjustable voltage amplitude, current amplitude, and timing characteristics through control signals. This dynamic configurability allows a single driver circuit to replace multiple fixed-function circuits, providing diverse test signal characteristics while reducing overall device complexity through parameter adjustment rather than structural multiplication.
4Ease of operation
If external switches are used for channel access, then calibration capability is provided, but switch resistance and loading on DUT pin increase
Solution Approach 1:
The patent provides multiple independent calibration access points that replicate the full DUT interface functionality. Each channel has its own dedicated calibration access that copies the complete signal path characteristics, allowing calibration without introducing external switches that would add resistance and loading. This copying approach enables direct calibration access while maintaining signal integrity.
Data Source
AI summary
A force-sense system can provide signals to, or receive signals from, a device under test (DUT) at a first DUT node. The system can include output buffer circuitry configured to provide a DUT signal to the DUT in response to a force control signal at a buffer control node, and controller circuitry configured to provide the force control signal at the buffer control node. The system can include bypass circuitry configured to selectively bypass the controller circuitry and provide an auxiliary control signal at the buffer control node. The auxiliary control signal can be used for system calibration. In an example, an external calibration circuit can provide the auxiliary control signal in response to information received from the DUT.


