Pin Electronics Timing Set Pre-loading for Test Channel Mapping
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Solution Overview
Problem
Circuit test systems face inefficiencies due to the need for frequent loading and reloading of timing sets when dynamically mapping test channels to varying sub-channels, leading to significant test time overhead, especially when using a switching matrix that requires calibration of multiple signal channels.
Innovation Solution
A method is introduced to analyze the test program and create a map of required timing sets for specific combinations of channels and sub-channels, pre-loading only the necessary sub-channel-specific timing sets into pin electronics, reducing the number of timing sets stored and minimizing the need for frequent loading and reloading during test execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all sub-channel-specific timing sets are stored in pin electronics, then complete calibration coverage is achieved, but device complexity and memory requirements increase significantly
Solution Approach 1:
The patent segments the complete set of timing sets into multiple groups, with only a subset pre-loaded into pin electronics memory at any given time. The system divides timing set management into local cached copies and external storage, reducing immediate memory requirements while maintaining access to all necessary calibration data through selective loading.
Solution Approach 2:
The patent performs preliminary analysis of the test program to identify which timing sets will be needed before test execution begins. This allows the system to pre-load only the necessary timing sets into pin electronics memory in advance, avoiding the need to store all possible timing sets simultaneously while ensuring required calibration data is immediately available.
2Adaptability or versatility
If timing sets are loaded dynamically during test execution, then adaptability to different test scenarios is improved, but test time overhead increases due to frequent loading and reloading
Solution Approach 1:
The patent analyzes the test program beforehand to determine the sequence and requirements of different test scenarios. Based on this analysis, it pre-loads the appropriate timing sets into pin electronics memory before test execution begins, eliminating the need for dynamic loading during testing and reducing test time overhead while maintaining adaptability to various test scenarios.
Solution Approach 2:
The patent ensures that timing sets required for different test scenarios are continuously available in memory by pre-loading them before test execution. This eliminates interruptions and waiting time associated with dynamic loading, allowing the test system to continuously operate without time losses from memory access operations.
3Adaptability or versatility
If a switching matrix is used to dynamically map test channels to sub-channels, then test channel versatility is improved, but the number of required timing sets and calibration complexity increase
Solution Approach 1:
The patent segments the large set of sub-channel-specific timing sets into smaller manageable groups, pre-loading only the relevant subset into pin electronics memory based on the current test channel configuration. This segmentation reduces the complexity of calibration data management while maintaining the versatility provided by the switching matrix for dynamic channel mapping.
Solution Approach 2:
The patent introduces an intermediary layer (the pin electronics with pre-loaded timing sets) between the switching matrix and the test execution. This intermediary caches the necessary calibration data locally, reducing the complexity of real-time calibration data management while preserving the full adaptability of the switching matrix for dynamic channel-to-sub-channel mapping.
Data Source
AI summary
In one embodiment, a method includes, providing a test program designed to control a circuit test system. The circuit test system has a plurality of test channels, each test channel of which is configured to be selectively coupled to a plurality of sub-channels under control of the test program. The method further includes 1) analyzing the test program to determine what combinations of channels, sub-channels and timing sets are required by the test program, and 2) in response to this analysis, creating a map of which timing sets, for which combinations of channels and sub-channels, should be pre-loaded into pin electronics that correspond to the test channels.