Pin-Level Stress Testing for Semiconductor Package Assembly Defects
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Solution Overview
Problem
Traditional high voltage stress testing (HVST) methods primarily focus on wafer-level defects and do not adequately address defects introduced during the semiconductor package assembly process, particularly in complex packages like ball grid arrays, leading to potential shorts between power and ground pins.
Innovation Solution
A method and system for stress testing packaged semiconductor devices that apply stress voltage to each pin individually, using a functional pattern to minimize test time, with all pins initially set to ground except one, which is stressed to its highest allowable voltage, followed by a mid-range voltage application to detect shorts between pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional high voltage stress test (HVST) is applied to stress only power pins with elevated voltage, then wafer-level defects affecting gate oxide and contacts can be accelerated, but defects introduced during package assembly process cannot be detected
Solution Approach 1:
The patent segments the testing approach by dividing pins into different categories (power pins, ground pins, and signal pins) and applying appropriate stress patterns to each category. This allows defects in package assembly to be detected across all pin types while maintaining the effectiveness of high voltage stress testing for wafer-level defects.
Solution Approach 2:
The testing system is designed to perform multiple functions: it can apply high voltage stress to power pins, ground pins, and signal pins using different stress patterns. This universal approach enables detection of both wafer-level defects and package assembly defects across all pin types, resolving the limitation of traditional HVST that only stressed power pins.
2Productivity
If inputs/outputs are grouped into two groups (evens and odds) stressed in parallel, then test time is reduced, but coverage for complex packages like ball grid arrays is inadequate
Solution Approach 1:
Instead of grouping pins into only two parallel groups (evens and odds), the patent segments pins into multiple categories based on their function and location (power pins, ground pins, signal pins). Each category can be stressed independently with appropriate patterns, ensuring comprehensive coverage of complex packages while maintaining efficient parallel testing.
Solution Approach 2:
The patent extends the testing approach from a single-dimensional grouping (even/odd) to a multi-dimensional classification system that considers pin function, location, and electrical characteristics. This allows for more sophisticated parallel stress patterns that achieve both reduced test time and improved defect detection coverage.
3Reliability
If stress voltage is applied to each pin individually one by one, then complete coverage of all pins is achieved, but test time increases significantly
Solution Approach 1:
The patent segments the pin population into functional groups (power pins, ground pins, signal pins) that can be stressed in parallel. Within each group, pins can be tested simultaneously using group-level stress patterns, achieving comprehensive coverage without the time penalty of sequential individual pin testing.
Solution Approach 2:
The patent merges the stress application for multiple pins by applying group-level stress patterns that simultaneously stress multiple pins within the same functional group. This combining approach maintains pin-level stress coverage while reducing test time through parallel execution of stress patterns across different pin groups.
Data Source
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AI summary
A method for stress testing a device under test (DUT) having a plurality of pins includes generating a stress test pattern which independently stresses each pin of the plurality of pins, wherein the stress test pattern includes a plurality of test vector, and applying each test vector to the plurality of pins for a predetermined amount of time. The method further includes, after applying all the test vectors of the stress test pattern, applying a programmable load to each pin independently and after applying each programmable load, comparing an output voltage of each pin to a predetermined voltage range to form an output vector for each pin.