Standard Cell Pin Modification for Routing Area
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Solution Overview
Problem
The increasing demand for scaled integrated circuits poses challenges in routing interconnects due to restrictions imposed by wire cuts placed by electronic design automation tools, which limit the availability of area for interconnects in integrated circuit layout designs.
Innovation Solution
Modifying the dimensions of standard cell pins to increase their distance from boundaries, thereby avoiding the placement of wire cuts and providing additional area for interconnect routing, while ensuring a minimum distance based on technology node-specific parameters to prevent electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire cuts are placed by electronic design automation tools to prevent electrical shorts, then electrical integrity is improved, but the area available for interconnect routing is reduced
Solution Approach 1:
The pin dimensions are modified in advance during the design phase to proactively prevent wire cut placement. By adjusting pin dimensions before routing, the design creates sufficient spacing that eliminates the need for wire cuts, thereby preserving routing area while maintaining electrical integrity
Solution Approach 2:
The physical dimensions of standard cell pins are changed to increase spacing between adjacent pins. This parameter modification (increasing distance between pins) prevents electrical shorts without requiring wire cuts, thus resolving the contradiction between reliability and routing area
2Area of stationary object
If pin dimensions are increased to provide more spacing, then area for interconnect routing is improved, but the standard cell layout complexity increases
Solution Approach 1:
Instead of uniformly increasing all pin dimensions across the entire standard cell library, the invention applies dimension modifications only to specific pins where spacing is insufficient. This localized approach increases routing area where needed while minimizing impact on overall layout complexity
Solution Approach 2:
Specific pin dimension parameters are adjusted within defined ranges to achieve adequate spacing. The modifications are constrained by technology node-specific parameters and minimum distance requirements, ensuring that complexity increases are controlled and manageable
Data Source
AI summary
The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.