Pin Multiplexing Arbiter Delay Register Bus Contention
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Solution Overview
Problem
Pin multiplexing techniques for I/O bus interfaces often result in bus contention due to differences in access times of external devices, which can be mitigated by reducing device frequency, but this compromises system performance.
Innovation Solution
A semiconductor device with a shared I/O multiplexer and arbiter that includes a delay register to manage the switching between external devices, ensuring proper timing to prevent bus contention by accounting for varying bus turn-around times through programmable delay values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If pin multiplexing is used to share I/O pins between multiple external devices, then pin resource utilization is improved, but bus contention occurs due to differences in access times of the external devices
Solution Approach 1:
The arbiter grants bus access to external devices in advance based on predetermined timing requirements. Before switching the multiplexed interface between devices, the arbiter proactively allocates bus access rights to ensure smooth transitions, preventing bus contention by preparing the access schedule beforehand rather than reacting to conflicts after they occur.
2Reliability
If buffering outputs or forcing lower frequency is used to counter bus contention, then bus contention is reduced, but overall system performance deteriorates
Solution Approach 1:
The arbiter dynamically adjusts bus access timing and duration for each external device based on their specific access time requirements. Rather than using fixed buffering or uniform frequency reduction, the system adaptively manages bus allocation in real-time, allowing each device to operate at its optimal speed while preventing contention through intelligent, dynamic scheduling.
Data Source
AI summary
A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.